214 lines
6.9 KiB
C++
214 lines
6.9 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Kevin Lim
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*/
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#include "arch/alpha/faults.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "base/trace.hh"
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#if FULL_SYSTEM
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#include "arch/alpha/ev5.hh"
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#else
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#include "sim/process.hh"
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#include "mem/page_table.hh"
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#endif
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namespace AlphaISA
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{
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FaultName MachineCheckFault::_name = "mchk";
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FaultVect MachineCheckFault::_vect = 0x0401;
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FaultStat MachineCheckFault::_count;
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FaultName AlignmentFault::_name = "unalign";
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FaultVect AlignmentFault::_vect = 0x0301;
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FaultStat AlignmentFault::_count;
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FaultName ResetFault::_name = "reset";
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FaultVect ResetFault::_vect = 0x0001;
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FaultStat ResetFault::_count;
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FaultName ArithmeticFault::_name = "arith";
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FaultVect ArithmeticFault::_vect = 0x0501;
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FaultStat ArithmeticFault::_count;
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#if !FULL_SYSTEM
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FaultName PageTableFault::_name = "page_table_fault";
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FaultVect PageTableFault::_vect = 0x0000;
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FaultStat PageTableFault::_count;
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#endif
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FaultName InterruptFault::_name = "interrupt";
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FaultVect InterruptFault::_vect = 0x0101;
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FaultStat InterruptFault::_count;
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultStat NDtbMissFault::_count;
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultStat PDtbMissFault::_count;
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FaultName DtbPageFault::_name = "dfault";
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultStat DtbPageFault::_count;
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FaultName DtbAcvFault::_name = "dfault";
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultStat DtbAcvFault::_count;
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FaultName DtbAlignmentFault::_name = "unalign";
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FaultVect DtbAlignmentFault::_vect = 0x0301;
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FaultStat DtbAlignmentFault::_count;
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FaultName ItbMissFault::_name = "itbmiss";
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultStat ItbMissFault::_count;
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FaultName ItbPageFault::_name = "itbmiss";
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultStat ItbPageFault::_count;
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultStat ItbAcvFault::_count;
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultStat UnimplementedOpcodeFault::_count;
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FaultName FloatEnableFault::_name = "fen";
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultStat FloatEnableFault::_count;
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FaultName PalFault::_name = "pal";
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FaultVect PalFault::_vect = 0x2001;
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FaultStat PalFault::_count;
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FaultName IntegerOverflowFault::_name = "intover";
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultStat IntegerOverflowFault::_count;
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#if FULL_SYSTEM
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void AlphaFault::invoke(ThreadContext * tc)
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{
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FaultBase::invoke(tc);
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countStat()++;
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// exception restart address
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if (setRestartAddress() || !(tc->readPC() & 0x3))
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tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
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if (skipFaultingInstruction()) {
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// traps... skip faulting instruction.
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tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
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tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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}
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tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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}
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void ArithmeticFault::invoke(ThreadContext * tc)
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{
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FaultBase::invoke(tc);
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panic("Arithmetic traps are unimplemented!");
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}
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void DtbFault::invoke(ThreadContext * tc)
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{
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// Set fault address and flags. Even though we're modeling an
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// EV5, we use the EV6 technique of not latching fault registers
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// on VPTE loads (instead of locking the registers until IPR_VA is
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// read, like the EV5). The EV6 approach is cleaner and seems to
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// work with EV5 PAL code, but not the other way around.
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if (!tc->misspeculating()
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&& !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
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// set VA register with faulting address
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tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
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// set MM_STAT register flags
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tc->setMiscReg(AlphaISA::IPR_MM_STAT,
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(((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
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| ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
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| (flags & 0x3f)));
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// set VA_FORM register with faulting formatted address
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tc->setMiscReg(AlphaISA::IPR_VA_FORM,
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tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
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}
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AlphaFault::invoke(tc);
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}
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void ItbFault::invoke(ThreadContext * tc)
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{
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if (!tc->misspeculating()) {
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tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
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tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
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tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
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(AlphaISA::VAddr(pc).vpn() << 3));
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}
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AlphaFault::invoke(tc);
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}
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#else //!FULL_SYSTEM
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void PageTableFault::invoke(ThreadContext *tc)
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{
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Process *p = tc->getProcessPtr();
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// address is higher than the stack region or in the current stack region
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if (vaddr > p->stack_base || vaddr > p->stack_min)
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FaultBase::invoke(tc);
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// We've accessed the next page
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if (vaddr > p->stack_min - PageBytes) {
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DPRINTF(Stack,
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"Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
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p->stack_min, p->stack_base, p->stack_min - PageBytes,
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p->stack_base, vaddr);
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p->stack_min -= PageBytes;
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if (p->stack_base - p->stack_min > 8*1024*1024)
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fatal("Over max stack size for one thread\n");
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p->pTable->allocate(p->stack_min, PageBytes);
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} else {
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warn("Page fault on address %#x\n", vaddr);
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FaultBase::invoke(tc);
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}
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}
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#endif
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} // namespace AlphaISA
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