gem5/src
Curtis Dunham 564482c782 sim: Reuse the same limit_event in simulate()
This patch accomplishes two things:
1. Makes simulate()'s GlobalSimLoopExitEvent a singleton reused
   across calls. This is slightly more efficient than recreating
   it every time.
2. Gives callers to simulate() (especially other simulators) a
   foolproof way of knowing that the simulation period ended
   successfully by hitting the limit event. They can call
   getLimitEvent() and compare it to the return
   value of simulate().

This change was motivated by an ongoing effort to integrate gem5
and SST, with SST as the master sim and gem5 as the slave sim.
2015-03-23 06:57:36 -04:00
..
arch arm: Share a port for the two table walker objects 2015-03-02 04:00:42 -05:00
base base: Add compiler macros to add deprecation warnings 2015-02-11 10:23:24 -05:00
cpu cpu: Fix TrafficGen message format 2015-03-19 04:06:12 -04:00
dev arm: Add a GICv2m device 2015-03-19 04:06:17 -04:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Move AddrRangeList from port.hh to addr_range.hh 2014-10-16 05:49:59 -04:00
mem mem: Tidy up Request 2015-03-23 06:57:34 -04:00
proto cpu: add support for outputing a protobuf formatted CPU trace 2015-02-16 03:32:38 -05:00
python base: Add XOR-based hashed address interleaving 2015-02-03 14:25:54 -05:00
sim sim: Reuse the same limit_event in simulate() 2015-03-23 06:57:36 -04:00
unittest test: Add a unittest for the BitUnion types. 2015-01-07 00:34:40 -08:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript base: Add compiler macros to add deprecation warnings 2015-02-11 10:23:24 -05:00