arm: Add a GICv2m device
This patch adds a new PIO-accessible GICv2m shim. This shim has a PIO slave port on one side, and SPI 'wires' on the other. It accepts MSIs from the system and triggers SPIs on the GIC. It is configurable with a number of frames, each of which has a number of SPIs and a base SPI offset. A Linux driver for GICv2m is available upstream.
This commit is contained in:
Matt Evans
parent
ec80224188
commit
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4 changed files with 310 additions and 1 deletions
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@ -1,4 +1,4 @@
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# Copyright (c) 2012 ARM Limited
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# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@ -37,6 +37,7 @@
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import SimObject
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from Device import PioDevice
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from Platform import Platform
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@ -58,3 +59,18 @@ class Pl390(BaseGic):
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cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
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int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
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it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
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class Gicv2mFrame(SimObject):
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type = 'Gicv2mFrame'
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cxx_header = "dev/arm/gic_v2m.hh"
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spi_base = Param.UInt32(0x0, "Frame SPI base number");
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spi_len = Param.UInt32(0x0, "Frame SPI total number");
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addr = Param.Addr("Address for frame PIO")
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class Gicv2m(PioDevice):
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type = 'Gicv2m'
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cxx_header = "dev/arm/gic_v2m.hh"
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pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
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gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
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frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
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@ -50,6 +50,7 @@ if env['TARGET_ISA'] == 'arm':
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Source('base_gic.cc')
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Source('generic_timer.cc')
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Source('gic_pl390.cc')
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Source('gic_v2m.cc')
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Source('pl011.cc')
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Source('pl111.cc')
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Source('hdlcd.cc')
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@ -65,6 +66,7 @@ if env['TARGET_ISA'] == 'arm':
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DebugFlag('AMBA')
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DebugFlag('HDLcd')
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DebugFlag('PL111')
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DebugFlag('GICV2M')
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DebugFlag('Pl050')
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DebugFlag('GIC')
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DebugFlag('RVCTRL')
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170
src/dev/arm/gic_v2m.cc
Normal file
170
src/dev/arm/gic_v2m.cc
Normal file
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@ -0,0 +1,170 @@
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/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Matt Evans
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*/
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/** @file
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* Implementiation of a GICv2m MSI shim.
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*
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* This shim adds MSI support to GICv2.
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*
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* This should be instantiated with the appropriate number of frames,
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* and SPI numbers thereof, to the system being modelled.
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*
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* For example, in RealView.py (or whichever board setup is used), instantiate:
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*
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* gicv2m = Gicv2m(frames=[
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* Gicv2mFrame(addr=0x12340000, spi_base=320, spi_len=64),
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* Gicv2mFrame(addr=0x12350000, spi_base=100, spi_len=32),
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* Gicv2mFrame(addr=0x12360000, spi_base=150, spi_len=16),
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* Gicv2mFrame(addr=0x12370000, spi_base=190, spi_len=8),
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* ])
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*
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*/
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#include "dev/arm/gic_v2m.hh"
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#include "base/bitunion.hh"
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#include "base/intmath.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/GICV2M.hh"
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#include "dev/io_device.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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Gicv2m *
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Gicv2mParams::create()
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{
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return new Gicv2m(this);
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}
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Gicv2mFrame *
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Gicv2mFrameParams::create()
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{
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return new Gicv2mFrame(this);
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}
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Gicv2m::Gicv2m(const Params *p)
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: PioDevice(p), pioDelay(p->pio_delay), frames(p->frames), gic(p->gic)
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{
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// Assert SPI ranges start at 32
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for (int i = 0; i < frames.size(); i++) {
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if (frames[i]->spi_base < 32)
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fatal("Gicv2m: Frame %d's SPI base (%d) is not in SPI space\n",
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i, frames[i]->spi_base);
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}
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unsigned int x = frames.size();
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fatal_if(!isPowerOf2(x), "Gicv2m: The v2m shim must be configured with "
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"a power-of-two number of frames\n");
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log2framenum = floorLog2(x);
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}
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AddrRangeList
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Gicv2m::getAddrRanges() const
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{
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AddrRangeList ranges;
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for (int i = 0; i < frames.size(); i++) {
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ranges.push_back(RangeSize(frames[i]->addr, FRAME_SIZE));
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}
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return ranges;
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}
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Tick
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Gicv2m::read(PacketPtr pkt)
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{
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int frame = frameFromAddr(pkt->getAddr());
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assert(frame >= 0);
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Addr offset = pkt->getAddr() - frames[frame]->addr;
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switch (offset) {
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case MSI_TYPER:
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pkt->set<uint32_t>((frames[frame]->spi_base << 16) |
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frames[frame]->spi_len);
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break;
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case PER_ID4:
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pkt->set<uint32_t>(0x4 | ((4+log2framenum) << 4));
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// Nr of 4KB blocks used by component. This is messy as frames are 64K
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// (16, ie 2^4) and we should assert we're given a Po2 number of frames.
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break;
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default:
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DPRINTF(GICV2M, "GICv2m: Read of unk reg %#x\n", offset);
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pkt->set<uint32_t>(0);
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};
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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Gicv2m::write(PacketPtr pkt)
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{
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int frame = frameFromAddr(pkt->getAddr());
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assert(frame >= 0);
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Addr offset = pkt->getAddr() - frames[frame]->addr;
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if (offset == MSI_SETSPI_NSR) {
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/* Is payload SPI number within range? */
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uint32_t m = pkt->get<uint32_t>();
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if (m >= frames[frame]->spi_base &&
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m < (frames[frame]->spi_base + frames[frame]->spi_len)) {
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DPRINTF(GICV2M, "GICv2m: Frame %d raising MSI %d\n", frame, m);
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gic->sendInt(m);
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}
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} else {
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DPRINTF(GICV2M, "GICv2m: Write of unk reg %#x\n", offset);
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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int
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Gicv2m::frameFromAddr(Addr a) const
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{
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for (int i = 0; i < frames.size(); i++) {
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if (a >= frames[i]->addr && a < (frames[i]->addr + FRAME_SIZE))
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return i;
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}
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return -1;
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}
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121
src/dev/arm/gic_v2m.hh
Normal file
121
src/dev/arm/gic_v2m.hh
Normal file
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@ -0,0 +1,121 @@
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/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Matt Evans
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*/
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/** @file
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* Implementiation of a GICv2m MSI shim.
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*
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* See gic_v2m.cc for an instantiation example.
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*/
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#ifndef __DEV_ARM_GIC_V2M_H__
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#define __DEV_ARM_GIC_V2M_H__
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#include "base/bitunion.hh"
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#include "cpu/intr_control.hh"
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#include "dev/arm/base_gic.hh"
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#include "dev/io_device.hh"
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#include "dev/platform.hh"
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#include "params/Gicv2m.hh"
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#include "params/Gicv2mFrame.hh"
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/**
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* Ultimately this class should be embedded in the Gicv2m class, but
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* this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame'
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* in namespace Gicv2m.
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*/
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class Gicv2mFrame : public SimObject
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{
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public:
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const Addr addr;
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const unsigned int spi_base;
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const unsigned int spi_len;
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typedef Gicv2mFrameParams Params;
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Gicv2mFrame(const Params *p) :
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SimObject(p), addr(p->addr), spi_base(p->spi_base), spi_len(p->spi_len)
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{}
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};
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class Gicv2m : public PioDevice
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{
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private:
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static const int FRAME_SIZE = 0x10000;
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static const int MSI_TYPER = 0x0008;
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static const int MSI_SETSPI_NSR = 0x0040;
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static const int PER_ID4 = 0x0fd0;
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/** Latency for an MMIO operation */
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const Tick pioDelay;
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/** A set of configured hardware frames */
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std::vector<Gicv2mFrame *> frames;
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/** Gic to which we fire interrupts */
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BaseGic *gic;
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/** Count of number of configured frames, as log2(frames) */
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unsigned int log2framenum;
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public:
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typedef Gicv2mParams Params;
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Gicv2m(const Params *p);
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/** @{ */
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/** Return the address ranges used by the Gicv2m
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* This is the set of frame addresses
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*/
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virtual AddrRangeList getAddrRanges() const;
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/** A PIO read to the device
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*/
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virtual Tick read(PacketPtr pkt);
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/** A PIO read to the device
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*/
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virtual Tick write(PacketPtr pkt);
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/** @} */
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private:
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/** Determine which frame a PIO access lands in
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*/
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int frameFromAddr(Addr a) const;
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};
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#endif //__DEV_ARM_GIC_V2M_H__
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