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arm: Remove the 'magic MSI register' in the GIC (PL390)

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This patch removes the code that added this magic register. A
follow-up patch provides a GICv2m MSI shim that gives the same
functionality in a standard ARM system architecture way.
This commit is contained in:
Matt Evans 2015-03-19 04:06:16 -04:00
parent 142ab40c4b
commit ec80224188
3 changed files with 1 additions and 81 deletions
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1
src/dev/arm/Gic.py
View file

@ -54,7 +54,6 @@ class Pl390(BaseGic):
dist_addr = Param.Addr(0x1f001000, "Address for distributor")
cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
msix_addr = Param.Addr(0x0, "Address for MSI-X register")
dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")

63
src/dev/arm/gic_pl390.cc
View file

@ -55,9 +55,7 @@ Pl390::Pl390(const Params *p)
: BaseGic(p), distAddr(p->dist_addr),
cpuAddr(p->cpu_addr), distPioDelay(p->dist_pio_delay),
cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
enabled(false), itLines(p->it_lines), irqEnable(false),
msixRegAddr(p->msix_addr),
msixReg(0x0)
enabled(false), itLines(p->it_lines), irqEnable(false)
{
itLinesLog2 = ceilLog2(itLines);
@ -113,10 +111,6 @@ Pl390::read(PacketPtr pkt)
return readDistributor(pkt);
else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
return readCpu(pkt);
else if (msixRegAddr != 0x0 &&
addr >= msixRegAddr &&
addr < msixRegAddr + MSIX_SIZE)
return readMsix(pkt);
else
panic("Read to unknown address %#x\n", pkt->getAddr());
}
@ -132,10 +126,6 @@ Pl390::write(PacketPtr pkt)
return writeDistributor(pkt);
else if (addr >= cpuAddr && addr < cpuAddr + CPU_SIZE)
return writeCpu(pkt);
else if (msixRegAddr != 0x0 &&
addr >= msixRegAddr &&
addr < msixRegAddr + MSIX_SIZE)
return writeMsix(pkt);
else
panic("Write to unknown address %#x\n", pkt->getAddr());
}
@ -357,26 +347,6 @@ Pl390::readCpu(PacketPtr pkt)
return cpuPioDelay;
}
Tick
Pl390::readMsix(PacketPtr pkt)
{
Addr daddr = pkt->getAddr() - msixRegAddr;
DPRINTF(GIC, "Gic MSIX read register %#x\n", daddr);
switch (daddr) {
case MSIX_SR:
pkt->set<uint32_t>(msixReg);
break;
default:
panic("Tried to read Gic MSIX register at offset %#x\n", daddr);
break;
}
pkt->makeAtomicResponse();
return distPioDelay;
}
Tick
Pl390::writeDistributor(PacketPtr pkt)
{
@ -571,30 +541,6 @@ Pl390::writeCpu(PacketPtr pkt)
return cpuPioDelay;
}
Tick
Pl390::writeMsix(PacketPtr pkt)
{
Addr daddr = pkt->getAddr() - msixRegAddr;
DPRINTF(GIC, "Gic MSI-X write register %#x data %d\n",
daddr, pkt->get<uint32_t>());
switch (daddr) {
case MSIX_SR:
// This value is little endian, just like the ARM guest
msixReg = pkt->get<uint32_t>();
pendingInt[intNumToWord(letoh(msixReg))] |= 1UL << intNumToBit(letoh(msixReg));
updateIntState(-1);
break;
default:
panic("Tried to write Gic MSI-X register at offset %#x\n", daddr);
break;
}
pkt->makeAtomicResponse();
return distPioDelay;
}
void
Pl390::softInt(int ctx_id, SWI swi)
{
@ -786,9 +732,6 @@ Pl390::getAddrRanges() const
AddrRangeList ranges;
ranges.push_back(RangeSize(distAddr, DIST_SIZE));
ranges.push_back(RangeSize(cpuAddr, CPU_SIZE));
if (msixRegAddr != 0) {
ranges.push_back(RangeSize(msixRegAddr, MSIX_SIZE));
}
return ranges;
}
@ -805,8 +748,6 @@ Pl390::serialize(std::ostream &os)
SERIALIZE_SCALAR(enabled);
SERIALIZE_SCALAR(itLines);
SERIALIZE_SCALAR(itLinesLog2);
SERIALIZE_SCALAR(msixRegAddr);
SERIALIZE_SCALAR(msixReg);
SERIALIZE_ARRAY(intEnabled, INT_BITS_MAX);
SERIALIZE_ARRAY(pendingInt, INT_BITS_MAX);
SERIALIZE_ARRAY(activeInt, INT_BITS_MAX);
@ -847,8 +788,6 @@ Pl390::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(enabled);
UNSERIALIZE_SCALAR(itLines);
UNSERIALIZE_SCALAR(itLinesLog2);
UNSERIALIZE_SCALAR(msixRegAddr);
UNSERIALIZE_SCALAR(msixReg);
UNSERIALIZE_ARRAY(intEnabled, INT_BITS_MAX);
UNSERIALIZE_ARRAY(pendingInt, INT_BITS_MAX);
UNSERIALIZE_ARRAY(activeInt, INT_BITS_MAX);

18
src/dev/arm/gic_pl390.hh
View file

@ -113,10 +113,6 @@ class Pl390 : public BaseGic
static const int INT_BITS_MAX = 32;
static const int INT_LINES_MAX = 1020;
/** MSI-X register offset and size */
static const int MSIX_SR = 0x0; // MSI register devices will write to
static const int MSIX_SIZE = 0x4; // Size of MSI-X register space
BitUnion32(SWI)
Bitfield<3,0> sgi_id;
Bitfield<23,16> cpu_list;
@ -211,10 +207,6 @@ class Pl390 : public BaseGic
/** IRQ Enable Used for debug */
bool irqEnable;
/** MSIX Register */
Addr msixRegAddr;
uint32_t msixReg;
/** software generated interrupt
* @param data data to decode that indicates which cpus to interrupt
*/
@ -322,11 +314,6 @@ class Pl390 : public BaseGic
*/
Tick readCpu(PacketPtr pkt);
/** Handle a read to the MSI-X register on the GIC
* @param pkt packet to respond to
*/
Tick readMsix(PacketPtr pkt);
/** Handle a write to the distributor poriton of the GIC
* @param pkt packet to respond to
*/
@ -336,11 +323,6 @@ class Pl390 : public BaseGic
* @param pkt packet to respond to
*/
Tick writeCpu(PacketPtr pkt);
/** Handle a write to the MSI-X register on the GIC
* @param pkt packet to process
*/
Tick writeMsix(PacketPtr pkt);
};
#endif //__DEV_ARM_GIC_H__