Erfan Azarkhish 100cbc9cf6 mem: hmc: top level design ... This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It highly reuses the existing components in gem5's general memory system with some small modifications. This changeset requires additional patches to model a complete HMC device. Committed by: Nilay Vaish <nilay@cs.wisc.edu>		2015-11-03 12:17:56 -06:00
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fs.py	mem: hmc: top level design	2015-11-03 12:17:56 -06:00
memcheck.py	mem: Add explicit Cache subclass and make BaseCache abstract	2015-08-21 07:03:23 -04:00
memtest.py	mem: Add explicit Cache subclass and make BaseCache abstract	2015-08-21 07:03:23 -04:00
read_config.py	config: Add the ability to read a config file using C++ and Python	2014-10-16 05:49:37 -04:00
ruby_direct_test.py	ruby: interface with classic memory controller	2014-11-06 05:42:21 -06:00
ruby_mem_test.py	mem: Move crossbar default latencies to subclasses	2015-03-02 04:00:47 -05:00
ruby_network_test.py	configs: network test: remove redundant physical memory	2015-07-21 10:08:25 -05:00
ruby_random_test.py	ruby: interface with classic memory controller	2014-11-06 05:42:21 -06:00
se.py	isa,cpu: Add support for FS SMT Interrupts	2015-09-30 11:14:19 -05:00