Kevin Lim 4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5 ... into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d		2006-09-30 23:43:23 -04:00
..
alpha_access.h	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
alpha_console.cc	Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.	2006-06-06 17:32:21 -04:00
alpha_console.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
baddev.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
baddev.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
disk_image.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
disk_image.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherbus.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherbus.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherdump.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherdump.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherint.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherint.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherlink.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherlink.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherpkt.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
etherpkt.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
ethertap.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
ethertap.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
i8254xGBe.cc	add boiler plate intel nic code	2006-09-18 20:12:45 -04:00
i8254xGBe.hh	add boiler plate intel nic code	2006-09-18 20:12:45 -04:00
i8254xGBe_defs.hh	add boiler plate intel nic code	2006-09-18 20:12:45 -04:00
ide_atareg.h	New directory structure:	2006-05-22 14:29:33 -04:00
ide_ctrl.cc	Need config read/write latency.	2006-07-27 16:43:02 -04:00
ide_ctrl.hh	Add default responder to bus	2006-07-06 14:41:01 -04:00
ide_disk.cc	fixes for gcc 4.1	2006-08-15 17:41:22 -04:00
ide_disk.hh	Merge ktlim@zamp:./local/clean/o3-merge/m5	2006-09-30 23:43:23 -04:00
ide_wdcreg.h	New directory structure:	2006-05-22 14:29:33 -04:00
io_device.cc	Move more common functionality into SimpleTimingPort,	2006-08-30 16:24:26 -07:00
io_device.hh	Move more common functionality into SimpleTimingPort,	2006-08-30 16:24:26 -07:00
isa_fake.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
isa_fake.hh	Fix up doxygen.	2006-08-14 19:25:07 -04:00
ns_gige.cc	Need config read/write latency.	2006-07-27 16:43:02 -04:00
ns_gige.hh	memory mode information now contained in system object	2006-07-12 20:22:07 -04:00
ns_gige_reg.h	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
pciconfigall.cc	Add default responder to bus	2006-07-06 14:41:01 -04:00
pciconfigall.hh	Add default responder to bus	2006-07-06 14:41:01 -04:00
pcidev.cc	add boiler plate intel nic code	2006-09-18 20:12:45 -04:00
pcidev.hh	Move more common functionality into SimpleTimingPort,	2006-08-30 16:24:26 -07:00
pcireg.h	Get rid of unneeded union.	2006-08-28 11:01:25 -07:00
pitreg.h	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
pktfifo.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
pktfifo.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
platform.cc	Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alpha/pagetable.hh and fixing up some includes	2006-08-15 04:46:51 -04:00
platform.hh	Add default responder to bus	2006-07-06 14:41:01 -04:00
rtcreg.h	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
simconsole.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
simconsole.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
simple_disk.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
simple_disk.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
sinic.cc	fixes for gcc 4.1	2006-08-15 17:41:22 -04:00
sinic.hh	memory mode information now contained in system object	2006-07-12 20:22:07 -04:00
sinicreg.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
tsunami.cc	Add default responder to bus	2006-07-06 14:41:01 -04:00
tsunami.hh	Fix up doxygen.	2006-08-14 19:25:07 -04:00
tsunami_cchip.cc	Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.	2006-06-06 17:32:21 -04:00
tsunami_cchip.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
tsunami_io.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
tsunami_io.hh	Fix up doxygen.	2006-08-14 19:25:07 -04:00
tsunami_pchip.cc	Add default responder to bus	2006-07-06 14:41:01 -04:00
tsunami_pchip.hh	Two minor FS compile fixes.	2006-07-06 16:26:44 -04:00
tsunamireg.h	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
uart.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
uart.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
uart8250.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
uart8250.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00