Nilay Vaish 4f4a710457 Config: corrects the way Ruby attaches to the DMA ports ... With recent changes to the memory system, a port cannot be assigned a peer port twice. While making use of the Ruby memory system in FS mode, DMA ports were assigned peer twice, once for the classic memory system and once for the Ruby memory system. This patch removes this double assignment of peer ports.		2012-04-05 11:09:19 -05:00
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Benchmarks.py	configs: fix minor config bugs posted on the mailing list	2012-02-12 17:18:53 -06:00
CacheConfig.py	x86: Fix switching of CPUs	2012-03-01 11:37:02 -06:00
Caches.py	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	2011-12-01 00:15:22 -08:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	Config: corrects the way Ruby attaches to the DMA ports	2012-04-05 11:09:19 -05:00
O3_ARM_v7a.py	prefetcher: Make prefetcher a sim object instead of it being a parameter on cache	2012-02-12 16:07:38 -06:00
Options.py	Config: Change the way options are added	2012-03-28 11:01:53 -05:00
Simulation.py	Config: Move setWorkCountOptions() to Simulation.py	2012-03-27 18:23:21 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00