gem5/src/arch/arm/isa
Steve Reinhardt 4d77ea7a57 cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical.  Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition.  It also moves those calls above
the translation calls to eliminate the crashes.
2010-03-23 08:50:57 -07:00
..
formats cpu: fix exec tracing memory corruption bug 2010-03-23 08:50:57 -07:00
bitfields.isa ARM: Begin implementing CP15 2009-11-17 18:02:09 -06:00
copyright.txt arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
decoder.isa ARM: Begin implementing CP15 2009-11-17 18:02:09 -06:00
includes.isa ARM: Make DataOps select from a set of ways to set the c and v flags. 2009-07-01 22:17:06 -07:00
main.isa ARM: Move util functions out of the isa desc. 2009-06-21 22:50:33 -07:00
operands.isa ARM: More accurately describe the effects of using the control operands. 2009-11-14 19:22:29 -08:00