gem5/python/m5/objects
Nathan Binkert 47ff0af17e Virtualize sinic
separate the rx thread and tx thread and get rid of the dedicated flag.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
    dedicated flag goes away, we have new individual flags for
    rx thread and tx thread
dev/sinic.cc:
    Virtualize sinic
    - The io registers are replicated many times in memory, allowing the NIC to
    differentiate among several virtual interfaces.
    - On the TX side, this allows multiple CPUs to initiate transmits at the same
    time without locking in the software.  If a partial packet is transmitted,
    then the state machine blocks waiting for that virtual interface to complete
    its packet.  Then the state machine will move on to the next virtual
    interface.  The commands are kept in fifo order.
    - On the RX side, multiple partial transmits can be simultaneously done.
    Though a packet does not deallocate its fifo space until all preceeding
    packets in the fifo are deallocated.  To enable multiple receives, it
    is necessary for each virtual nic to keep its own information about its
    progress through the state machine.
dev/sinic.hh:
    Virtualize sinic
    Receive state must be virtualized since we allow the receipt of packets in
    parallel.
dev/sinicreg.hh:
    Virtualize sinic
    separate rx thread and tx thread
    create a soft interrupt and add a command to trigger it.
    pad out the reserved bits in the RxDone and TxDone regs

--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
2005-11-25 13:33:36 -05:00
..
AlphaConsole.py Allow CPUs to specify their own CPU ids. 2005-06-29 01:20:41 -04:00
AlphaFullCPU.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
AlphaTLB.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
BadDevice.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
BaseCache.py Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
BaseCPU.py Allow CPUs to specify their own CPU ids. 2005-06-29 01:20:41 -04:00
Bus.py Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
CoherenceProtocol.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Device.py io_bus is split out into pio_bus and dma_bus so that any device 2005-11-20 16:57:53 -05:00
DiskImage.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Ethernet.py Virtualize sinic 2005-11-25 13:33:36 -05:00
Ide.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
IntrControl.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
MemTest.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Pci.py BARs now of type MemorySize32 2005-11-21 00:02:39 -05:00
PhysicalMemory.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Platform.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Process.py Add executable parameter to LiveProcess. This allows the argv[0] value to 2005-10-01 16:02:47 -04:00
Repl.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Root.py Add execution trace object to Root. 2005-10-06 13:50:13 -04:00
SimConsole.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
SimpleDisk.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
System.py BaseSystem was renamed to System 2005-06-09 15:09:35 -04:00
Tsunami.py Changes for getting FreeBSD to run. 2005-08-15 16:59:58 -04:00
Uart.py make all of the turbolaser stuff only compile if ALPHA_TLASER 2005-06-05 01:24:17 -04:00