gem5/src
Geoffrey Blake 1e1cd2dc01 arm, dev: Fix flash model serialization code typos
The flash model has typos in its serialization code for
unknownPages, locationTable, blockValidEntries, and blockEmptyEntries
arrays where it would save each entry in the array under the same
name in the checkpoint.  This patch fixes these typos.
2015-11-22 05:10:19 -05:00
..
arch arm: Fix fplib 128-bit shift operators 2015-11-22 05:10:18 -05:00
base misc: Appease clang static analyzer 2015-11-06 03:26:16 -05:00
cpu cpu: Fix base FP and CC register index in o3 insertThread() 2015-11-22 05:10:19 -05:00
dev arm, dev: Fix flash model serialization code typos 2015-11-22 05:10:19 -05:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
mem arm: Add missing explicit overrides for classic caches 2015-11-15 21:28:00 +00:00
proto cpu: add support for outputing a protobuf formatted CPU trace 2015-02-16 03:32:38 -05:00
python sim: print pid in output header 2015-10-06 17:26:50 -07:00
sim misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
unittest base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00