Bjoern A. Zeeb f0786704db arm: AArch64 report cache size correctly when reading CTR_EL0 ... Trying to read MISCREG_CTR_EL0 on AArch64 returned 0 as is was not implmemented. With that an operating system relying on the cache line sizes reported in order to manage the caches would (a) panic given the returned value 0 is not valid (high bit is RES1) or (b) worst case would assume a cache line size of 4 doing a tremendous amount of extra instruction work (including fetching). Return the same values as for ARMv7 as the fields seem to be the same, or RES0/1 seem to be reported accordingly for AArch64 In collaboration with: Andrew Turner Testing Done: Checked on FreeBSD boots with extra printfs; also observed a reduction of a factor of about 10 in instruction fetches for a simple micro-test. Reviewed at http://reviews.gem5.org/r/3667/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>		2017-02-09 18:54:28 -05:00
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alpha	syscall_emul: [patch 4/22] remove redundant M5_pid field from process	2016-11-09 14:27:40 -06:00
arm	arm: AArch64 report cache size correctly when reading CTR_EL0	2017-02-09 18:54:28 -05:00
generic	style: [patch 1/22] use /r/3648/ to reorganize includes	2016-11-09 14:27:37 -06:00
hsail	hsail: disable asserts to allow immediate operands i.e. 0 with loads	2016-12-02 18:01:58 -05:00
mips	style: [patch 3/22] reduce include dependencies in some headers	2016-11-09 14:27:40 -06:00
null	cpu,isa,mem: Add per-thread wakeup logic	2015-09-30 11:14:19 -05:00
power	style: [patch 3/22] reduce include dependencies in some headers	2016-11-09 14:27:40 -06:00
riscv	riscv: Fix crash when syscall argument reg index is too high	2017-01-27 15:05:01 -06:00
sparc	syscall_emul: [patch 4/22] remove redundant M5_pid field from process	2016-11-09 14:27:40 -06:00
x86	style: [patch 3/22] reduce include dependencies in some headers	2016-11-09 14:27:40 -06:00
isa_parser.py	cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass	2016-10-15 14:58:45 -05:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF	2016-10-26 22:47:38 -04:00