3a1428365a
readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason.
1205 lines
34 KiB
C++
1205 lines
34 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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def template PanicExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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panic("Execute function executed when it shouldn't be!\n");
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return NoFault;
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}
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}};
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def template PanicInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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panic("InitiateAcc function executed when it shouldn't be!\n");
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return NoFault;
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}
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}};
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def template PanicCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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panic("CompleteAcc function executed when it shouldn't be!\n");
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return NoFault;
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}
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}};
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def template SwapExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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uint64_t memData = 0;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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%(preacc_code)s;
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
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&memData);
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template SwapInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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uint64_t memData = 0;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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%(preacc_code)s;
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if (fault == NoFault) {
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fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
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&memData);
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template SwapCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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// ARM instructions will not have a pkt if the predicate is false
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getMem(pkt, Mem, traceData);
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uint64_t memData = Mem;
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%(postacc_code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template LoadExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template NeonLoadExecute {{
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template <class Element>
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Fault %(class_name)s<Element>::execute(
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%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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MemUnion memUnion;
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uint8_t *dataPtr = memUnion.bytes;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA,
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memAccessFlags, NULL);
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template NeonStoreExecute {{
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template <class Element>
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Fault %(class_name)s<Element>::execute(
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%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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MemUnion memUnion;
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uint8_t *dataPtr = memUnion.bytes;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->writeMem(dataPtr, %(size)d, EA,
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memAccessFlags, NULL);
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template StoreExExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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uint64_t writeResult;
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
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&writeResult);
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template StoreExInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
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NULL);
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
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NULL);
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template NeonStoreInitiateAcc {{
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template <class Element>
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Fault %(class_name)s<Element>::initiateAcc(
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%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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MemUnion memUnion;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->writeMem(memUnion.bytes, %(size)d, EA,
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memAccessFlags, NULL);
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template LoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_src_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template NeonLoadInitiateAcc {{
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template <class Element>
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Fault %(class_name)s<Element>::initiateAcc(
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%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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MemUnion memUnion;
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uint8_t *dataPtr = memUnion.bytes;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
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}
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} else {
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xc->setPredicate(false);
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}
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return fault;
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}
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}};
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def template LoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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// ARM instructions will not have a pkt if the predicate is false
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getMem(pkt, Mem, traceData);
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template NeonLoadCompleteAcc {{
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template <class Element>
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Fault %(class_name)s<Element>::completeAcc(
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PacketPtr pkt, %(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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|
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%(mem_decl)s;
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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// ARM instructions will not have a pkt if the predicate is false
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MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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|
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def template StoreCompleteAcc {{
|
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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return NoFault;
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}
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}};
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|
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def template NeonStoreCompleteAcc {{
|
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template <class Element>
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Fault %(class_name)s<Element>::completeAcc(
|
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PacketPtr pkt, %(CPU_exec_context)s *xc,
|
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Trace::InstRecord *traceData) const
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{
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return NoFault;
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}
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}};
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|
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def template StoreExCompleteAcc {{
|
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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|
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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uint64_t writeResult = pkt->req->getExtraData();
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%(postacc_code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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|
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def template RfeDeclare {{
|
|
/**
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|
* Static instruction class for "%(mnemonic)s".
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*/
|
|
class %(class_name)s : public %(base_class)s
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|
{
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|
public:
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|
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/// Constructor.
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%(class_name)s(ExtMachInst machInst,
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uint32_t _base, int _mode, bool _wb);
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|
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%(BasicExecDeclare)s
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|
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
|
|
}};
|
|
|
|
def template SrsDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _regMode, int _mode, bool _wb);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template SwapDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _op1, uint32_t _base);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template LoadStoreDImmDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _dest2,
|
|
uint32_t _base, bool _add, int32_t _imm);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template StoreExDImmDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _result, uint32_t _dest, uint32_t _dest2,
|
|
uint32_t _base, bool _add, int32_t _imm);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template LoadStoreImmDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template StoreExImmDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _result, uint32_t _dest, uint32_t _base,
|
|
bool _add, int32_t _imm);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template StoreDRegDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _dest2,
|
|
uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType,
|
|
uint32_t _index);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template StoreRegDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType,
|
|
uint32_t _index);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template LoadDRegDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _dest2,
|
|
uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType,
|
|
uint32_t _index);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template LoadRegDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType,
|
|
uint32_t _index);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template LoadImmDeclare {{
|
|
/**
|
|
* Static instruction class for "%(mnemonic)s".
|
|
*/
|
|
class %(class_name)s : public %(base_class)s
|
|
{
|
|
public:
|
|
|
|
/// Constructor.
|
|
%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
|
|
|
|
%(BasicExecDeclare)s
|
|
|
|
%(InitiateAccDeclare)s
|
|
|
|
%(CompleteAccDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template InitiateAccDeclare {{
|
|
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
|
|
}};
|
|
|
|
def template CompleteAccDeclare {{
|
|
Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
|
|
}};
|
|
|
|
def template RfeConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _base, int _mode, bool _wb)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_base, (AddrMode)_mode, _wb)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
|
|
int uopIdx = 0;
|
|
uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
|
|
uops[uopIdx]->setDelayedCommit();
|
|
#if %(use_wb)d
|
|
uops[++uopIdx] = new %(wb_decl)s;
|
|
uops[uopIdx]->setDelayedCommit();
|
|
#endif
|
|
#if %(use_pc)d
|
|
uops[++uopIdx] = new %(pc_decl)s;
|
|
#endif
|
|
uops[uopIdx]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template SrsConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _regMode, int _mode, bool _wb)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(OperatingMode)_regMode, (AddrMode)_mode, _wb)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template SwapConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _op1, uint32_t _base)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreDImmConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _dest2,
|
|
uint32_t _base, bool _add, int32_t _imm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_dest2,
|
|
(IntRegIndex)_base, _add, _imm)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template StoreExDImmConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _result, uint32_t _dest, uint32_t _dest2,
|
|
uint32_t _base, bool _add, int32_t _imm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_result,
|
|
(IntRegIndex)_dest, (IntRegIndex)_dest2,
|
|
(IntRegIndex)_base, _add, _imm)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
|
|
_base, _add, _imm);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreImmConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template StoreExImmConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _result, uint32_t _dest, uint32_t _base,
|
|
bool _add, int32_t _imm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_result, (IntRegIndex)_dest,
|
|
(IntRegIndex)_base, _add, _imm)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _result, _dest,
|
|
_base, _add, _imm);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template StoreDRegConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_dest2,
|
|
(IntRegIndex)_base, _add,
|
|
_shiftAmt, (ArmShiftType)_shiftType,
|
|
(IntRegIndex)_index)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
|
|
_shiftAmt, _shiftType, _index);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template StoreRegConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_base, _add,
|
|
_shiftAmt, (ArmShiftType)_shiftType,
|
|
(IntRegIndex)_index)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
|
|
_shiftAmt, _shiftType, _index);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template LoadDRegConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_dest2,
|
|
(IntRegIndex)_base, _add,
|
|
_shiftAmt, (ArmShiftType)_shiftType,
|
|
(IntRegIndex)_index)
|
|
{
|
|
%(constructor)s;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
if ((_dest == _index) || (_dest2 == _index)) {
|
|
IntRegIndex wbIndexReg = INTREG_UREG0;
|
|
uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
|
|
_shiftAmt, _shiftType, _index);
|
|
uops[1]->setDelayedCommit();
|
|
uops[2] = new %(wb_decl)s;
|
|
uops[2]->setLastMicroop();
|
|
} else {
|
|
IntRegIndex wbIndexReg = index;
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
|
|
_shiftAmt, _shiftType, _index);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
}
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template LoadRegConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add,
|
|
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_base, _add,
|
|
_shiftAmt, (ArmShiftType)_shiftType,
|
|
(IntRegIndex)_index)
|
|
{
|
|
%(constructor)s;
|
|
bool conditional = false;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
conditional = true;
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
if (_dest == INTREG_PC) {
|
|
IntRegIndex wbIndexReg = index;
|
|
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
|
|
_shiftAmt, _shiftType, _index);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setDelayedCommit();
|
|
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
|
|
uops[2]->setFlag(StaticInst::IsControl);
|
|
uops[2]->setFlag(StaticInst::IsIndirectControl);
|
|
if (conditional)
|
|
uops[2]->setFlag(StaticInst::IsCondControl);
|
|
else
|
|
uops[2]->setFlag(StaticInst::IsUncondControl);
|
|
uops[2]->setLastMicroop();
|
|
} else if(_dest == _index) {
|
|
IntRegIndex wbIndexReg = INTREG_UREG0;
|
|
uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
|
|
_shiftAmt, _shiftType, _index);
|
|
uops[1]->setDelayedCommit();
|
|
uops[2] = new %(wb_decl)s;
|
|
uops[2]->setLastMicroop();
|
|
} else {
|
|
IntRegIndex wbIndexReg = index;
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
|
|
_shiftAmt, _shiftType, _index);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
|
|
}
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template LoadImmConstructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
|
|
{
|
|
%(constructor)s;
|
|
bool conditional = false;
|
|
if (!(condCode == COND_AL || condCode == COND_UC)) {
|
|
conditional = true;
|
|
for (int x = 0; x < _numDestRegs; x++) {
|
|
_srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
|
|
}
|
|
}
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
if (_dest == INTREG_PC) {
|
|
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
|
|
_imm);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setDelayedCommit();
|
|
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
|
|
uops[2]->setFlag(StaticInst::IsControl);
|
|
uops[2]->setFlag(StaticInst::IsIndirectControl);
|
|
if (conditional)
|
|
uops[2]->setFlag(StaticInst::IsCondControl);
|
|
else
|
|
uops[2]->setFlag(StaticInst::IsUncondControl);
|
|
if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
|
|
uops[2]->setFlag(StaticInst::IsReturn);
|
|
uops[2]->setLastMicroop();
|
|
} else {
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
}
|
|
#endif
|
|
}
|
|
}};
|
|
|