5c7ebee434
This patch moves the 16x APIC clock divider to the Python code to avoid the post-instantiation modifications to the clock. The x86 APIC was the only object setting the clock after creation time and this required some custom functionality and configuration. With this patch, the clock multiplier is moved to the Python code and the objects are instantiated with the appropriate clock.
793 lines
26 KiB
C++
793 lines
26 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/regs/apic.hh"
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#include "arch/x86/interrupts.hh"
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#include "arch/x86/intmessage.hh"
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#include "cpu/base.hh"
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#include "debug/LocalApic.hh"
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#include "dev/x86/i82094aa.hh"
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#include "dev/x86/pc.hh"
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#include "dev/x86/south_bridge.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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#include "sim/full_system.hh"
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int
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divideFromConf(uint32_t conf)
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{
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// This figures out what division we want from the division configuration
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// register in the local APIC. The encoding is a little odd but it can
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// be deciphered fairly easily.
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int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
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shift = (shift + 1) % 8;
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return 1 << shift;
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}
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namespace X86ISA
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{
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ApicRegIndex
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decodeAddr(Addr paddr)
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{
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ApicRegIndex regNum;
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paddr &= ~mask(3);
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switch (paddr)
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{
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case 0x20:
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regNum = APIC_ID;
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break;
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case 0x30:
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regNum = APIC_VERSION;
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break;
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case 0x80:
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regNum = APIC_TASK_PRIORITY;
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break;
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case 0x90:
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regNum = APIC_ARBITRATION_PRIORITY;
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break;
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case 0xA0:
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regNum = APIC_PROCESSOR_PRIORITY;
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break;
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case 0xB0:
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regNum = APIC_EOI;
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break;
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case 0xD0:
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regNum = APIC_LOGICAL_DESTINATION;
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break;
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case 0xE0:
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regNum = APIC_DESTINATION_FORMAT;
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break;
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case 0xF0:
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regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
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break;
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case 0x100:
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case 0x108:
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case 0x110:
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case 0x118:
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case 0x120:
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case 0x128:
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case 0x130:
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case 0x138:
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case 0x140:
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case 0x148:
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case 0x150:
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case 0x158:
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case 0x160:
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case 0x168:
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case 0x170:
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case 0x178:
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regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
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break;
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case 0x180:
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case 0x188:
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case 0x190:
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case 0x198:
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case 0x1A0:
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case 0x1A8:
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case 0x1B0:
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case 0x1B8:
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case 0x1C0:
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case 0x1C8:
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case 0x1D0:
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case 0x1D8:
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case 0x1E0:
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case 0x1E8:
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case 0x1F0:
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case 0x1F8:
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regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
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break;
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case 0x200:
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case 0x208:
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case 0x210:
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case 0x218:
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case 0x220:
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case 0x228:
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case 0x230:
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case 0x238:
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case 0x240:
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case 0x248:
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case 0x250:
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case 0x258:
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case 0x260:
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case 0x268:
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case 0x270:
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case 0x278:
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regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
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break;
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case 0x280:
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regNum = APIC_ERROR_STATUS;
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break;
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case 0x300:
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regNum = APIC_INTERRUPT_COMMAND_LOW;
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break;
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case 0x310:
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regNum = APIC_INTERRUPT_COMMAND_HIGH;
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break;
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case 0x320:
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regNum = APIC_LVT_TIMER;
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break;
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case 0x330:
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regNum = APIC_LVT_THERMAL_SENSOR;
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break;
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case 0x340:
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regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
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break;
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case 0x350:
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regNum = APIC_LVT_LINT0;
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break;
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case 0x360:
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regNum = APIC_LVT_LINT1;
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break;
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case 0x370:
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regNum = APIC_LVT_ERROR;
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break;
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case 0x380:
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regNum = APIC_INITIAL_COUNT;
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break;
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case 0x390:
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regNum = APIC_CURRENT_COUNT;
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break;
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case 0x3E0:
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regNum = APIC_DIVIDE_CONFIGURATION;
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break;
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default:
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// A reserved register field.
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panic("Accessed reserved register field %#x.\n", paddr);
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break;
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}
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return regNum;
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}
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}
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Tick
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X86ISA::Interrupts::read(PacketPtr pkt)
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{
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Addr offset = pkt->getAddr() - pioAddr;
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//Make sure we're at least only accessing one register.
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if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
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panic("Accessed more than one register at a time in the APIC!\n");
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ApicRegIndex reg = decodeAddr(offset);
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uint32_t val = htog(readReg(reg));
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DPRINTF(LocalApic,
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"Reading Local APIC register %d at offset %#x as %#x.\n",
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reg, offset, val);
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pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
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pkt->makeAtomicResponse();
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return latency;
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}
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Tick
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X86ISA::Interrupts::write(PacketPtr pkt)
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{
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Addr offset = pkt->getAddr() - pioAddr;
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//Make sure we're at least only accessing one register.
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if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
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panic("Accessed more than one register at a time in the APIC!\n");
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ApicRegIndex reg = decodeAddr(offset);
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uint32_t val = regs[reg];
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pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
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DPRINTF(LocalApic,
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"Writing Local APIC register %d at offset %#x as %#x.\n",
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reg, offset, gtoh(val));
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setReg(reg, gtoh(val));
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pkt->makeAtomicResponse();
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return latency;
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}
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void
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X86ISA::Interrupts::requestInterrupt(uint8_t vector,
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uint8_t deliveryMode, bool level)
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{
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/*
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* Fixed and lowest-priority delivery mode interrupts are handled
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* using the IRR/ISR registers, checking against the TPR, etc.
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* The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
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*/
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if (deliveryMode == DeliveryMode::Fixed ||
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deliveryMode == DeliveryMode::LowestPriority) {
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DPRINTF(LocalApic, "Interrupt is an %s.\n",
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DeliveryMode::names[deliveryMode]);
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// Queue up the interrupt in the IRR.
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if (vector > IRRV)
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IRRV = vector;
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if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
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setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
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if (level) {
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setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
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} else {
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clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
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}
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}
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} else if (!DeliveryMode::isReserved(deliveryMode)) {
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DPRINTF(LocalApic, "Interrupt is an %s.\n",
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DeliveryMode::names[deliveryMode]);
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if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
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pendingUnmaskableInt = pendingSmi = true;
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smiVector = vector;
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} else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
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pendingUnmaskableInt = pendingNmi = true;
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nmiVector = vector;
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} else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
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pendingExtInt = true;
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extIntVector = vector;
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} else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
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pendingUnmaskableInt = pendingInit = true;
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initVector = vector;
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} else if (deliveryMode == DeliveryMode::SIPI &&
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!pendingStartup && !startedUp) {
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pendingUnmaskableInt = pendingStartup = true;
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startupVector = vector;
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}
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}
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if (FullSystem)
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cpu->wakeup();
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}
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void
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X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
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{
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assert(newCPU);
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if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
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panic("Local APICs can't be moved between CPUs"
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" with different IDs.\n");
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}
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cpu = newCPU;
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initialApicId = cpu->cpuId();
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regs[APIC_ID] = (initialApicId << 24);
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pioAddr = x86LocalAPICAddress(initialApicId, 0);
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}
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void
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X86ISA::Interrupts::init()
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{
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//
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// The local apic must register its address ranges on both its pio port
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// via the basicpiodevice(piodevice) init() function and its int port
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// that it inherited from IntDev. Note IntDev is not a SimObject itself.
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//
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BasicPioDevice::init();
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IntDev::init();
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// the slave port has a range so inform the connected master
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intSlavePort.sendRangeChange();
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}
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Tick
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X86ISA::Interrupts::recvMessage(PacketPtr pkt)
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{
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Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
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assert(pkt->cmd == MemCmd::MessageReq);
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switch(offset)
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{
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case 0:
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{
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TriggerIntMessage message = pkt->get<TriggerIntMessage>();
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DPRINTF(LocalApic,
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"Got Trigger Interrupt message with vector %#x.\n",
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message.vector);
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requestInterrupt(message.vector,
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message.deliveryMode, message.trigger);
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}
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break;
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default:
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panic("Local apic got unknown interrupt message at offset %#x.\n",
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offset);
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break;
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}
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pkt->makeAtomicResponse();
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return latency;
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}
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Tick
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X86ISA::Interrupts::recvResponse(PacketPtr pkt)
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{
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assert(!pkt->isError());
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assert(pkt->cmd == MemCmd::MessageResp);
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if (--pendingIPIs == 0) {
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InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
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// Record that the ICR is now idle.
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low.deliveryStatus = 0;
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regs[APIC_INTERRUPT_COMMAND_LOW] = low;
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}
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DPRINTF(LocalApic, "ICR is now idle.\n");
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return 0;
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}
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AddrRangeList
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X86ISA::Interrupts::getAddrRanges() const
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{
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AddrRangeList ranges;
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AddrRange range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
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x86LocalAPICAddress(initialApicId, 0) +
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PageBytes);
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ranges.push_back(range);
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return ranges;
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}
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AddrRangeList
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X86ISA::Interrupts::getIntAddrRange() const
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{
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AddrRangeList ranges;
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ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
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x86InterruptAddress(initialApicId, 0) +
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PhysAddrAPICRangeSize));
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return ranges;
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}
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uint32_t
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X86ISA::Interrupts::readReg(ApicRegIndex reg)
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{
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if (reg >= APIC_TRIGGER_MODE(0) &&
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reg <= APIC_TRIGGER_MODE(15)) {
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panic("Local APIC Trigger Mode registers are unimplemented.\n");
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}
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switch (reg) {
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case APIC_ARBITRATION_PRIORITY:
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panic("Local APIC Arbitration Priority register unimplemented.\n");
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break;
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case APIC_PROCESSOR_PRIORITY:
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panic("Local APIC Processor Priority register unimplemented.\n");
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break;
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case APIC_ERROR_STATUS:
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regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
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break;
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case APIC_CURRENT_COUNT:
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{
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if (apicTimerEvent.scheduled()) {
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// Compute how many m5 ticks happen per count.
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uint64_t ticksPerCount = clockPeriod() *
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divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
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// Compute how many m5 ticks are left.
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uint64_t val = apicTimerEvent.when() - curTick();
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// Turn that into a count.
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val = (val + ticksPerCount - 1) / ticksPerCount;
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return val;
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} else {
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return 0;
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}
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}
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default:
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break;
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}
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return regs[reg];
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}
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void
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X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
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{
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uint32_t newVal = val;
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if (reg >= APIC_IN_SERVICE(0) &&
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reg <= APIC_IN_SERVICE(15)) {
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panic("Local APIC In-Service registers are unimplemented.\n");
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}
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if (reg >= APIC_TRIGGER_MODE(0) &&
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reg <= APIC_TRIGGER_MODE(15)) {
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panic("Local APIC Trigger Mode registers are unimplemented.\n");
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}
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if (reg >= APIC_INTERRUPT_REQUEST(0) &&
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reg <= APIC_INTERRUPT_REQUEST(15)) {
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panic("Local APIC Interrupt Request registers "
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"are unimplemented.\n");
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}
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switch (reg) {
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case APIC_ID:
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newVal = val & 0xFF;
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break;
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case APIC_VERSION:
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// The Local APIC Version register is read only.
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return;
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case APIC_TASK_PRIORITY:
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newVal = val & 0xFF;
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break;
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case APIC_ARBITRATION_PRIORITY:
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panic("Local APIC Arbitration Priority register unimplemented.\n");
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break;
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case APIC_PROCESSOR_PRIORITY:
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panic("Local APIC Processor Priority register unimplemented.\n");
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break;
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case APIC_EOI:
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// Remove the interrupt that just completed from the local apic state.
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clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
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updateISRV();
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return;
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case APIC_LOGICAL_DESTINATION:
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newVal = val & 0xFF000000;
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break;
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case APIC_DESTINATION_FORMAT:
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newVal = val | 0x0FFFFFFF;
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break;
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case APIC_SPURIOUS_INTERRUPT_VECTOR:
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regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
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regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
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if (val & (1 << 9))
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warn("Focus processor checking not implemented.\n");
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break;
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case APIC_ERROR_STATUS:
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{
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if (regs[APIC_INTERNAL_STATE] & 0x1) {
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regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
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newVal = 0;
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} else {
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regs[APIC_INTERNAL_STATE] |= ULL(0x1);
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return;
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}
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}
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break;
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case APIC_INTERRUPT_COMMAND_LOW:
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{
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InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
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// Check if we're already sending an IPI.
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if (low.deliveryStatus) {
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newVal = low;
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break;
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}
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low = val;
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InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
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// Record that an IPI is being sent.
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low.deliveryStatus = 1;
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TriggerIntMessage message = 0;
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message.destination = high.destination;
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message.vector = low.vector;
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message.deliveryMode = low.deliveryMode;
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message.destMode = low.destMode;
|
|
message.level = low.level;
|
|
message.trigger = low.trigger;
|
|
bool timing(sys->isTimingMode());
|
|
// Be careful no updates of the delivery status bit get lost.
|
|
regs[APIC_INTERRUPT_COMMAND_LOW] = low;
|
|
ApicList apics;
|
|
int numContexts = sys->numContexts();
|
|
switch (low.destShorthand) {
|
|
case 0:
|
|
if (message.deliveryMode == DeliveryMode::LowestPriority) {
|
|
panic("Lowest priority delivery mode "
|
|
"IPIs aren't implemented.\n");
|
|
}
|
|
if (message.destMode == 1) {
|
|
int dest = message.destination;
|
|
hack_once("Assuming logical destinations are 1 << id.\n");
|
|
for (int i = 0; i < numContexts; i++) {
|
|
if (dest & 0x1)
|
|
apics.push_back(i);
|
|
dest = dest >> 1;
|
|
}
|
|
} else {
|
|
if (message.destination == 0xFF) {
|
|
for (int i = 0; i < numContexts; i++) {
|
|
if (i == initialApicId) {
|
|
requestInterrupt(message.vector,
|
|
message.deliveryMode, message.trigger);
|
|
} else {
|
|
apics.push_back(i);
|
|
}
|
|
}
|
|
} else {
|
|
if (message.destination == initialApicId) {
|
|
requestInterrupt(message.vector,
|
|
message.deliveryMode, message.trigger);
|
|
} else {
|
|
apics.push_back(message.destination);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case 1:
|
|
newVal = val;
|
|
requestInterrupt(message.vector,
|
|
message.deliveryMode, message.trigger);
|
|
break;
|
|
case 2:
|
|
requestInterrupt(message.vector,
|
|
message.deliveryMode, message.trigger);
|
|
// Fall through
|
|
case 3:
|
|
{
|
|
for (int i = 0; i < numContexts; i++) {
|
|
if (i != initialApicId) {
|
|
apics.push_back(i);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
pendingIPIs += apics.size();
|
|
intMasterPort.sendMessage(apics, message, timing);
|
|
newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
|
|
}
|
|
break;
|
|
case APIC_LVT_TIMER:
|
|
case APIC_LVT_THERMAL_SENSOR:
|
|
case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
|
|
case APIC_LVT_LINT0:
|
|
case APIC_LVT_LINT1:
|
|
case APIC_LVT_ERROR:
|
|
{
|
|
uint64_t readOnlyMask = (1 << 12) | (1 << 14);
|
|
newVal = (val & ~readOnlyMask) |
|
|
(regs[reg] & readOnlyMask);
|
|
}
|
|
break;
|
|
case APIC_INITIAL_COUNT:
|
|
{
|
|
newVal = bits(val, 31, 0);
|
|
// Compute how many timer ticks we're being programmed for.
|
|
uint64_t newCount = newVal *
|
|
(divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
|
|
// Schedule on the edge of the next tick plus the new count.
|
|
Tick offset = curTick() % clockPeriod();
|
|
if (offset) {
|
|
reschedule(apicTimerEvent,
|
|
curTick() + (newCount + 1) *
|
|
clockPeriod() - offset, true);
|
|
} else {
|
|
reschedule(apicTimerEvent,
|
|
curTick() + newCount *
|
|
clockPeriod(), true);
|
|
}
|
|
}
|
|
break;
|
|
case APIC_CURRENT_COUNT:
|
|
//Local APIC Current Count register is read only.
|
|
return;
|
|
case APIC_DIVIDE_CONFIGURATION:
|
|
newVal = val & 0xB;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
regs[reg] = newVal;
|
|
return;
|
|
}
|
|
|
|
|
|
X86ISA::Interrupts::Interrupts(Params * p) :
|
|
BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
|
|
apicTimerEvent(this),
|
|
pendingSmi(false), smiVector(0),
|
|
pendingNmi(false), nmiVector(0),
|
|
pendingExtInt(false), extIntVector(0),
|
|
pendingInit(false), initVector(0),
|
|
pendingStartup(false), startupVector(0),
|
|
startedUp(false), pendingUnmaskableInt(false),
|
|
pendingIPIs(0), cpu(NULL),
|
|
intSlavePort(name() + ".int_slave", this, this, latency)
|
|
{
|
|
pioSize = PageBytes;
|
|
memset(regs, 0, sizeof(regs));
|
|
//Set the local apic DFR to the flat model.
|
|
regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
|
|
ISRV = 0;
|
|
IRRV = 0;
|
|
}
|
|
|
|
|
|
bool
|
|
X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
|
|
{
|
|
RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
|
|
if (pendingUnmaskableInt) {
|
|
DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
|
|
return true;
|
|
}
|
|
if (rflags.intf) {
|
|
if (pendingExtInt) {
|
|
DPRINTF(LocalApic, "Reported pending external interrupt.\n");
|
|
return true;
|
|
}
|
|
if (IRRV > ISRV && bits(IRRV, 7, 4) >
|
|
bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
|
|
DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
Fault
|
|
X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
|
|
{
|
|
assert(checkInterrupts(tc));
|
|
// These are all probably fairly uncommon, so we'll make them easier to
|
|
// check for.
|
|
if (pendingUnmaskableInt) {
|
|
if (pendingSmi) {
|
|
DPRINTF(LocalApic, "Generated SMI fault object.\n");
|
|
return new SystemManagementInterrupt();
|
|
} else if (pendingNmi) {
|
|
DPRINTF(LocalApic, "Generated NMI fault object.\n");
|
|
return new NonMaskableInterrupt(nmiVector);
|
|
} else if (pendingInit) {
|
|
DPRINTF(LocalApic, "Generated INIT fault object.\n");
|
|
return new InitInterrupt(initVector);
|
|
} else if (pendingStartup) {
|
|
DPRINTF(LocalApic, "Generating SIPI fault object.\n");
|
|
return new StartupInterrupt(startupVector);
|
|
} else {
|
|
panic("pendingUnmaskableInt set, but no unmaskable "
|
|
"ints were pending.\n");
|
|
return NoFault;
|
|
}
|
|
} else if (pendingExtInt) {
|
|
DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
|
|
return new ExternalInterrupt(extIntVector);
|
|
} else {
|
|
DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
|
|
// The only thing left are fixed and lowest priority interrupts.
|
|
return new ExternalInterrupt(IRRV);
|
|
}
|
|
}
|
|
|
|
void
|
|
X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
|
|
{
|
|
assert(checkInterrupts(tc));
|
|
if (pendingUnmaskableInt) {
|
|
if (pendingSmi) {
|
|
DPRINTF(LocalApic, "SMI sent to core.\n");
|
|
pendingSmi = false;
|
|
} else if (pendingNmi) {
|
|
DPRINTF(LocalApic, "NMI sent to core.\n");
|
|
pendingNmi = false;
|
|
} else if (pendingInit) {
|
|
DPRINTF(LocalApic, "Init sent to core.\n");
|
|
pendingInit = false;
|
|
startedUp = false;
|
|
} else if (pendingStartup) {
|
|
DPRINTF(LocalApic, "SIPI sent to core.\n");
|
|
pendingStartup = false;
|
|
startedUp = true;
|
|
}
|
|
if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
|
|
pendingUnmaskableInt = false;
|
|
} else if (pendingExtInt) {
|
|
pendingExtInt = false;
|
|
} else {
|
|
DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
|
|
// Mark the interrupt as "in service".
|
|
ISRV = IRRV;
|
|
setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
|
|
// Clear it out of the IRR.
|
|
clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
|
|
updateIRRV();
|
|
}
|
|
}
|
|
|
|
void
|
|
X86ISA::Interrupts::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
|
|
SERIALIZE_SCALAR(pendingSmi);
|
|
SERIALIZE_SCALAR(smiVector);
|
|
SERIALIZE_SCALAR(pendingNmi);
|
|
SERIALIZE_SCALAR(nmiVector);
|
|
SERIALIZE_SCALAR(pendingExtInt);
|
|
SERIALIZE_SCALAR(extIntVector);
|
|
SERIALIZE_SCALAR(pendingInit);
|
|
SERIALIZE_SCALAR(initVector);
|
|
SERIALIZE_SCALAR(pendingStartup);
|
|
SERIALIZE_SCALAR(startupVector);
|
|
SERIALIZE_SCALAR(startedUp);
|
|
SERIALIZE_SCALAR(pendingUnmaskableInt);
|
|
SERIALIZE_SCALAR(pendingIPIs);
|
|
SERIALIZE_SCALAR(IRRV);
|
|
SERIALIZE_SCALAR(ISRV);
|
|
bool apicTimerEventScheduled = apicTimerEvent.scheduled();
|
|
SERIALIZE_SCALAR(apicTimerEventScheduled);
|
|
Tick apicTimerEventTick = apicTimerEvent.when();
|
|
SERIALIZE_SCALAR(apicTimerEventTick);
|
|
}
|
|
|
|
void
|
|
X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
|
|
UNSERIALIZE_SCALAR(pendingSmi);
|
|
UNSERIALIZE_SCALAR(smiVector);
|
|
UNSERIALIZE_SCALAR(pendingNmi);
|
|
UNSERIALIZE_SCALAR(nmiVector);
|
|
UNSERIALIZE_SCALAR(pendingExtInt);
|
|
UNSERIALIZE_SCALAR(extIntVector);
|
|
UNSERIALIZE_SCALAR(pendingInit);
|
|
UNSERIALIZE_SCALAR(initVector);
|
|
UNSERIALIZE_SCALAR(pendingStartup);
|
|
UNSERIALIZE_SCALAR(startupVector);
|
|
UNSERIALIZE_SCALAR(startedUp);
|
|
UNSERIALIZE_SCALAR(pendingUnmaskableInt);
|
|
UNSERIALIZE_SCALAR(pendingIPIs);
|
|
UNSERIALIZE_SCALAR(IRRV);
|
|
UNSERIALIZE_SCALAR(ISRV);
|
|
bool apicTimerEventScheduled;
|
|
UNSERIALIZE_SCALAR(apicTimerEventScheduled);
|
|
if (apicTimerEventScheduled) {
|
|
Tick apicTimerEventTick;
|
|
UNSERIALIZE_SCALAR(apicTimerEventTick);
|
|
if (apicTimerEvent.scheduled()) {
|
|
reschedule(apicTimerEvent, apicTimerEventTick, true);
|
|
} else {
|
|
schedule(apicTimerEvent, apicTimerEventTick);
|
|
}
|
|
}
|
|
}
|
|
|
|
X86ISA::Interrupts *
|
|
X86LocalApicParams::create()
|
|
{
|
|
return new X86ISA::Interrupts(this);
|
|
}
|