ac161c1d72
This patch takes the Linux thread info support scattered across different ISA implementations (currently in ARM, ALPHA, and MIPS), and unifies them into a single file. Adds a few more helper functions to read out TGID, mm, etc. ISA-specific information (e.g., ALPHA PCBB register) is now moved to the corresponding isa_traits.hh files.
133 lines
4.8 KiB
C++
133 lines
4.8 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Stephen Hines
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*/
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#ifndef __ARCH_ARM_ISA_TRAITS_HH__
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#define __ARCH_ARM_ISA_TRAITS_HH__
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#include "arch/arm/types.hh"
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#include "base/types.hh"
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#include "cpu/static_inst_fwd.hh"
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namespace LittleEndianGuest {}
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#define TARGET_ARM
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namespace ArmISA
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{
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using namespace LittleEndianGuest;
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StaticInstPtr decodeInst(ExtMachInst);
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// ARM DOES NOT have a delay slot
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#define ISA_HAS_DELAY_SLOT 0
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const Addr PageShift = 12;
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const Addr PageBytes = ULL(1) << PageShift;
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const Addr Page_Mask = ~(PageBytes - 1);
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const Addr PageOffset = PageBytes - 1;
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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const Addr PteShift = 3;
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const Addr NPtePageShift = PageShift - PteShift;
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const Addr NPtePage = ULL(1) << NPtePageShift;
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const Addr PteMask = NPtePage - 1;
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//// All 'Mapped' segments go through the TLB
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//// All other segments are translated by dropping the MSB, to give
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//// the corresponding physical address
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// User Segment - Mapped
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const Addr USegBase = ULL(0x0);
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const Addr USegEnd = ULL(0x7FFFFFFF);
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const unsigned VABits = 32;
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const unsigned PABits = 32; // Is this correct?
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const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
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const Addr VAddrUnImplMask = ~VAddrImplMask;
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inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
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inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
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inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
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const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
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// return a no-op instruction... used for instruction fetch faults
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const ExtMachInst NoopMachInst = 0x01E320F000ULL;
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const int LogVMPageSize = 12; // 4K bytes
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const int VMPageSize = (1 << LogVMPageSize);
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// Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
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const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
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const int MachineBytes = 4;
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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const uint32_t HighVecs = 0xFFFF0000;
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// Memory accesses cannot be unaligned
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const bool HasUnalignedMemAcc = true;
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const bool CurThreadInfoImplemented = false;
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const int CurThreadInfoReg = -1;
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enum InterruptTypes
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{
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INT_RST,
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INT_ABT,
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INT_IRQ,
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INT_FIQ,
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INT_SEV, // Special interrupt for recieving SEV's
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NumInterruptTypes
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};
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} // namespace ArmISA
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using namespace ArmISA;
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#endif // __ARCH_ARM_ISA_TRAITS_HH__
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