309e1d8193
TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.
arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.
--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
74 lines
3.2 KiB
Python
74 lines
3.2 KiB
Python
# Copyright (c) 2003-2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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################
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# CpuModel class
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#
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# The CpuModel class encapsulates everything the ISA parser needs to
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# know about a particular CPU model.
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class CpuModel:
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# Dict of available CPU model objects. Accessible as CpuModel.dict.
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dict = {}
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# Constructor. Automatically adds models to CpuModel.dict.
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def __init__(self, name, filename, includes, strings):
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self.name = name
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self.filename = filename # filename for output exec code
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self.includes = includes # include files needed in exec file
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# The 'strings' dict holds all the per-CPU symbols we can
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# substitute into templates etc.
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self.strings = strings
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# Add self to dict
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CpuModel.dict[name] = self
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#
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# Define CPU models.
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#
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# Parameters are:
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# - name of model
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# - filename for generated ISA execution file
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# - includes needed for generated ISA execution file
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# - substitution strings for ISA description templates
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#
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CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc',
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'#include "cpu/simple/atomic.hh"',
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{ 'CPU_exec_context': 'AtomicSimpleCPU' })
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CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc',
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'#include "cpu/simple/timing.hh"',
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{ 'CPU_exec_context': 'TimingSimpleCPU' })
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CpuModel('FastCPU', 'fast_cpu_exec.cc',
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'#include "cpu/fast/cpu.hh"',
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{ 'CPU_exec_context': 'FastCPU' })
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CpuModel('FullCPU', 'full_cpu_exec.cc',
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'#include "encumbered/cpu/full/dyn_inst.hh"',
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{ 'CPU_exec_context': 'DynInst' })
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CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
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'#include "cpu/o3/alpha_dyn_inst.hh"',
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{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
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