Ali Saidi d0ea8ff088 The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter. ... In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather than creating a new one each time. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/cache_impl.hh: only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc) --HG-- extra : convert_revision : 6a9e3e96f51cedaab6de1b36cf317203899a3716		2007-04-04 13:56:38 -04:00
..
cache	The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.	2007-04-04 13:56:38 -04:00
config	Backing in more changsets, getting closer to compile	2006-06-28 14:35:00 -04:00
bridge.cc	Update bus bridges now that snoop ranges are passed properly	2006-11-14 01:12:52 -05:00
bridge.hh	Use PacketPtr everywhere	2006-10-20 00:10:12 -07:00
bus.cc	The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.	2007-04-04 13:56:38 -04:00
bus.hh	The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.	2007-04-04 13:56:38 -04:00
dram.cc	make our code a little more standards compliant	2007-01-26 18:48:51 -05:00
dram.hh	Use PacketPtr everywhere	2006-10-20 00:10:12 -07:00
mem_object.cc	stop m5 from leaking like a sieve	2007-03-08 18:57:15 -05:00
mem_object.hh	stop m5 from leaking like a sieve	2007-03-08 18:57:15 -05:00
packet.cc	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
packet.hh	Move all of the parameters of the Root SimObject so they are	2007-03-06 11:13:43 -08:00
packet_access.hh	Make byteswap work correctly on Twin??_t types.	2007-03-07 17:46:04 +00:00
page_table.cc	Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.	2007-03-07 20:04:46 +00:00
page_table.hh	add code to serialize se structures. Lisa is working on the python side of things and will test	2006-10-17 19:38:36 -04:00
physical.cc	some forgotten commits	2007-02-12 18:40:08 -05:00
physical.hh	rename store conditional stuff as extra data so it can be used for conditional swaps as well	2007-02-12 13:06:30 -05:00
port.cc	The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.	2007-04-04 13:56:38 -04:00
port.hh	Two fixes:	2007-03-09 10:06:09 -05:00
port_impl.hh	Put the ProcessInfo and StackTrace objects into the ISA namespaces.	2006-11-08 00:52:04 -05:00
request.hh	Move all of the parameters of the Root SimObject so they are	2007-03-06 11:13:43 -08:00
SConscript	Rework the way SCons recurses into subdirectories, making it	2007-03-10 23:00:54 -08:00
tport.cc	Make memory commands dense again to avoid cache stat table explosion.	2007-02-07 10:53:37 -08:00
tport.hh	Merge ktlim@zizzer:/bk/newmem	2006-10-31 14:37:19 -05:00
translating_port.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
translating_port.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
vport.cc	implement vtophys and 32bit gdb support	2007-02-18 19:57:46 -05:00
vport.hh	implement vtophys and 32bit gdb support	2007-02-18 19:57:46 -05:00