2885 lines
330 KiB
Text
2885 lines
330 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000108 # Number of seconds simulated
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sim_ticks 107711000 # Number of ticks simulated
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final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 152784 # Simulator instruction rate (inst/s)
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host_op_rate 152784 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 16568657 # Simulator tick rate (ticks/s)
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host_mem_usage 311444 # Number of bytes of host memory used
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host_seconds 6.50 # Real time elapsed on the host
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sim_insts 993230 # Number of instructions simulated
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sim_ops 993230 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 42560 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 665 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 666 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 114 # Per bank write bursts
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system.physmem.perBankRdBursts::1 42 # Per bank write bursts
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system.physmem.perBankRdBursts::2 30 # Per bank write bursts
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system.physmem.perBankRdBursts::3 60 # Per bank write bursts
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system.physmem.perBankRdBursts::4 66 # Per bank write bursts
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system.physmem.perBankRdBursts::5 27 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24 # Per bank write bursts
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system.physmem.perBankRdBursts::8 7 # Per bank write bursts
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system.physmem.perBankRdBursts::9 28 # Per bank write bursts
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system.physmem.perBankRdBursts::10 23 # Per bank write bursts
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system.physmem.perBankRdBursts::11 13 # Per bank write bursts
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system.physmem.perBankRdBursts::12 61 # Per bank write bursts
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system.physmem.perBankRdBursts::13 38 # Per bank write bursts
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system.physmem.perBankRdBursts::14 18 # Per bank write bursts
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system.physmem.perBankRdBursts::15 97 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 107683000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 666 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation
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system.physmem.totQLat 6590000 # Total ticks spent queuing
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system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 3.09 # Data bus utilization in percentage
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system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 510 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 161686.19 # Average gap between requests
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system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ)
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system.physmem_0.averagePower 749.440907 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states
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system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ)
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|
system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 729.430757 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu0.branchPred.lookups 81565 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.workload.num_syscalls 89 # Number of system calls
|
|
system.cpu0.numCycles 215423 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing
|
|
system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename
|
|
system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups
|
|
system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 188787 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 2.057901 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.125475 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 4227 2.24% 20.05% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 74093 39.25% 59.30% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 1618 0.86% 99.20% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 402 0.21% 99.88% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued
|
|
system.cpu0.iq.rate 1.803452 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 73578 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 76909 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 74891 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 1.798759 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 229361 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 453252 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 221341 # Number of memory references committed
|
|
system.cpu0.commit.loads 147223 # Number of loads committed
|
|
system.cpu0.commit.membars 84 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 76005 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 305598 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 223 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached
|
|
system.cpu0.rob.rob_reads 651013 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 935136 # The number of ROB writes
|
|
system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.committedInsts 380431 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 693268 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 312587 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
|
|
system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.replacements 2 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits
|
|
system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
|
|
system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 149410 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses
|
|
system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
|
|
system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1102 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1102 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1102 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1102 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16913500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 16913500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34798980 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 34798980 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 51712480 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 51712480 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 51712480 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 51712480 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 76436 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 76436 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74076 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 74076 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 150512 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 150512 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 150512 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 150512 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007156 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.007156 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007492 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.007492 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007322 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.007322 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007322 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.007322 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30920.475320 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30920.475320 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62700.864865 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 62700.864865 # average WriteReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 46926.025408 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 46926.025408 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 1 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 365 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 377 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 377 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 742 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 742 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 742 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 742 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6860000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8493000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8493000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15353000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 15353000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15353000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 15353000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002381 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002381 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002403 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002403 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37692.307692 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37692.307692 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47713.483146 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47713.483146 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 315 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.163907 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471023 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.471023 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 5949 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 784 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 784 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 784 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 784 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40406000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 40406000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 40406000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 40406000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 40406000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 40406000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51538.265306 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 51538.265306 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 51538.265306 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 51538.265306 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 176 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 176 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 176 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 176 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31294000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 53924 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu1.numCycles 162664 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename
|
|
system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups
|
|
system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued
|
|
system.cpu1.iq.rate 1.453419 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 38619 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 48027 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 37584 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 1.447253 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 134020 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 265858 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 114070 # Number of memory references committed
|
|
system.cpu1.commit.loads 77284 # Number of loads committed
|
|
system.cpu1.commit.membars 4232 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 46981 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 183171 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.50% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 81516 30.66% 86.16% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 36786 13.84% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 265858 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 1310 # number cycles where commit BW limit reached
|
|
system.cpu1.rob.rob_reads 431808 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 561746 # The number of ROB writes
|
|
system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 6008 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 223857 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 223857 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 0.726642 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 0.726642 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 1.376193 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 1.376193 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 409049 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 191377 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 118040 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu1.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 25.752806 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 42910 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 1479.655172 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.752806 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050298 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.050298 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 330593 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 330593 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 45309 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 45309 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 36557 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 36557 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 81866 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 81866 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 81866 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 81866 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 489 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 489 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 159 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 159 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 648 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 648 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 648 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 648 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9556000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 9556000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3376000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 3376000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 667000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 667000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 12932000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 12932000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 12932000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 12932000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 45798 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 45798 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 36716 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 36716 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 82514 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 82514 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 82514 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 82514 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010677 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.010677 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004331 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.004331 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007853 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.007853 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007853 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.007853 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19541.922290 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19541.922290 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21232.704403 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21232.704403 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12127.272727 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 12127.272727 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 19956.790123 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 19956.790123 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 325 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 378 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 378 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2051500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2051500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1754500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 383 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 19439 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 581 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.branchPred.lookups 55489 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu2.numCycles 162291 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename
|
|
system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers
|
|
system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups
|
|
system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued
|
|
system.cpu2.iq.rate 1.508309 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 40321 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 49723 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 39200 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.501993 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 138958 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 275802 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 118948 # Number of memory references committed
|
|
system.cpu2.commit.loads 80570 # Number of loads committed
|
|
system.cpu2.commit.membars 4324 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 48669 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 189737 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached
|
|
system.cpu2.rob.rob_reads 445356 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 582010 # The number of ROB writes
|
|
system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 232019 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 423842 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 197927 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu2.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use
|
|
system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
|
|
system.cpu2.dcache.tags.tag_accesses 343879 # Number of tag accesses
|
|
system.cpu2.dcache.tags.data_accesses 343879 # Number of data accesses
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 47002 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 47002 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 38151 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 38151 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 85153 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 85153 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 85153 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 85153 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 527 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 527 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 686 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 686 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 686 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 686 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9963000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 9963000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 4178000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 4178000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 670500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 670500 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 14141000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 14141000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 14141000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 14141000 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 47529 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 47529 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 38310 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 38310 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 85839 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 85839 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 85839 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 85839 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.011088 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.011088 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004150 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.004150 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007992 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.007992 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007992 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.007992 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18905.123340 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 18905.123340 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 26276.729560 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 26276.729560 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11973.214286 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 11973.214286 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 20613.702624 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 20613.702624 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 367 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 51 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::cpu2.data 418 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::total 418 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::cpu2.data 418 # number of overall MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::total 418 # number of overall MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1620500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1620500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2159500 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2159500 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 614500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 614500 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3780000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 3780000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3780000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 3780000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003366 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003366 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002819 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002819 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.003122 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.003122 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10128.125000 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10128.125000 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19995.370370 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19995.370370 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10973.214286 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10973.214286 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.icache.tags.replacements 386 # number of replacements
|
|
system.cpu2.icache.tags.tagsinuse 80.953803 # Cycle average of tags in use
|
|
system.cpu2.icache.tags.total_refs 19454 # Total number of references to valid blocks.
|
|
system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.tags.avg_refs 38.908000 # Average number of references to valid blocks.
|
|
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.tags.occ_blocks::cpu2.inst 80.953803 # Average occupied blocks per requestor
|
|
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.158113 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_percent::total 0.158113 # Average percentage of cache occupancy
|
|
system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id
|
|
system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses
|
|
system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 19454 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 573 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.branchPred.lookups 42820 # Number of BP lookups
|
|
system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted
|
|
system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect
|
|
system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups
|
|
system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits
|
|
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage
|
|
system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target.
|
|
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
|
|
system.cpu3.numCycles 161928 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps
|
|
system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched
|
|
system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle
|
|
system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle
|
|
system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked
|
|
system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running
|
|
system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking
|
|
system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing
|
|
system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode
|
|
system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing
|
|
system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle
|
|
system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking
|
|
system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running
|
|
system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename
|
|
system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full
|
|
system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full
|
|
system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers
|
|
system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups
|
|
system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed
|
|
system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed
|
|
system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed
|
|
system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer
|
|
system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores.
|
|
system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued
|
|
system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle
|
|
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued
|
|
system.cpu3.iq.rate 1.068166 # Inst issue rate
|
|
system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested
|
|
system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads
|
|
system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes
|
|
system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses
|
|
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses
|
|
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed
|
|
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations
|
|
system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions
|
|
system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu3.iew.exec_nop 27464 # number of nop insts executed
|
|
system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed
|
|
system.cpu3.iew.exec_branches 36861 # Number of branches executed
|
|
system.cpu3.iew.exec_stores 22696 # Number of stores executed
|
|
system.cpu3.iew.exec_rate 1.062126 # Inst execution rate
|
|
system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back
|
|
system.cpu3.iew.wb_producers 92998 # num instructions producing a value
|
|
system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value
|
|
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle
|
|
system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back
|
|
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit
|
|
system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle
|
|
system.cpu3.commit.committedInsts 191557 # Number of instructions committed
|
|
system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed
|
|
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.refs 73159 # Number of memory references committed
|
|
system.cpu3.commit.loads 51261 # Number of loads committed
|
|
system.cpu3.commit.membars 7996 # Number of memory barriers committed
|
|
system.cpu3.commit.branches 35851 # Number of branches committed
|
|
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu3.commit.int_insts 131131 # Number of committed integer instructions.
|
|
system.cpu3.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntAlu 83764 43.73% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemRead 59257 30.93% 88.57% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::MemWrite 21898 11.43% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu3.commit.op_class_0::total 191557 # Class of committed instruction
|
|
system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached
|
|
system.cpu3.rob.rob_reads 361140 # The number of ROB reads
|
|
system.cpu3.rob.rob_writes 412450 # The number of ROB writes
|
|
system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu3.committedInsts 156923 # Number of Instructions Simulated
|
|
system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated
|
|
system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads
|
|
system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads
|
|
system.cpu3.int_regfile_reads 285937 # number of integer regfile reads
|
|
system.cpu3.int_regfile_writes 135307 # number of integer regfile writes
|
|
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads
|
|
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu3.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use
|
|
system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045192 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
|
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
|
|
system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses
|
|
system.cpu3.dcache.tags.data_accesses 226271 # Number of data accesses
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 34144 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 21673 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 21673 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 55817 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 55817 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 55817 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 55817 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 154 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 154 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 617 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 617 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 617 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 617 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7346500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 7346500 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3280500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 3280500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 658000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 658000 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 10627000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 10627000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 10627000 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 10627000 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 34607 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 34607 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 21827 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 21827 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 56434 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 56434 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 56434 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.013379 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.732394 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.010933 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.010933 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 17223.662885 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 17223.662885 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 299 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::cpu3.data 351 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::cpu3.data 351 # number of overall MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 164 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 266 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 266 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1762500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1762500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1886000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1886000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 606000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 606000 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3648500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 3648500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3648500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 3648500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004739 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004739 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004673 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004673 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.732394 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.004713 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.004713 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10746.951220 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10746.951220 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18490.196078 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18490.196078 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11653.846154 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11653.846154 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.icache.tags.replacements 384 # number of replacements
|
|
system.cpu3.icache.tags.tagsinuse 77.554391 # Cycle average of tags in use
|
|
system.cpu3.icache.tags.total_refs 27370 # Total number of references to valid blocks.
|
|
system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.tags.avg_refs 54.959839 # Average number of references to valid blocks.
|
|
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.554391 # Average occupied blocks per requestor
|
|
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151473 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_percent::total 0.151473 # Average percentage of cache occupancy
|
|
system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id
|
|
system.cpu3.icache.tags.tag_accesses 28439 # Number of tag accesses
|
|
system.cpu3.icache.tags.data_accesses 28439 # Number of data accesses
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 27370 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 27370 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 27370 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 27370 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 27370 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 27370 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 571 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 571 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 571 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 571 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 571 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 571 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7675000 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 7675000 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 7675000 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 7675000 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 7675000 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 7675000 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 27941 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 27941 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 27941 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 27941 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 27941 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 27941 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020436 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.020436 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020436 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.020436 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020436 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.020436 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13441.330998 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 13441.330998 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 13441.330998 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 13441.330998 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 73 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::cpu3.inst 73 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::cpu3.inst 73 # number of overall MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6616000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 6616000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6616000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 6616000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6616000 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 6616000 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017823 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.017823 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.017823 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13285.140562 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 0 # number of replacements
|
|
system.l2c.tags.tagsinuse 419.148333 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 2348 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 4.413534 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 0.788271 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 288.012358 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 58.076849 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 62.302913 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 5.322223 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 3.076380 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 0.717940 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.inst 0.174188 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu3.data 0.677210 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.000951 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.inst 0.000003 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 25610 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 25610 # Number of data accesses
|
|
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 409 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu2.inst 490 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 490 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1670 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 246 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 409 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 490 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 493 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
|
system.l2c.overall_hits::total 1670 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 87 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 87 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 679 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 362 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 169 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 87 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 10 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 5 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
|
system.l2c.overall_misses::total 679 # number of overall misses
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 7619000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 1485500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 1133500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 11297000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27679000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6525500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 707500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 342000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 35254000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 5980500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 540500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu2.data 96500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu3.data 82500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 6700000 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 27679000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 13599500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 6525500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1599500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 707500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1582000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 342000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 1216000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 53251000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 27679000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 13599500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 6525500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1599500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 707500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1582000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 342000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 1216000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 53251000 # number of overall miss cycles
|
|
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 608 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 496 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu2.inst 500 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu3.inst 498 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 2102 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 80 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 12 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu2.data 12 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu3.data 12 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 116 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 608 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 496 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 500 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2349 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 608 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 496 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 500 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2349 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.966667 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.175403 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.020000 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.175403 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.020000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.175403 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.020000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.010040 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.289059 # miss rate for overall accesses
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81053.191489 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 94458.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 86236.641221 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76461.325967 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 75005.747126 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70750 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 68400 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 75978.448276 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79740 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77214.285714 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 82500 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 79761.904762 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 76461.325967 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 80470.414201 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 75005.747126 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 79975 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 70750 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 121692.307692 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 68400 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 93538.461538 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 78425.625920 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 76461.325967 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 80470.414201 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 75005.747126 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 79975 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 70750 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 121692.307692 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 68400 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 93538.461538 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 78425.625920 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 27 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 21 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 87 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 361 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 83 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 2 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 451 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 7 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 1 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 83 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 5 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 2 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 666 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 83 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 5 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 2 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 666 # number of overall MSHR misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 586500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 413500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 436000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 457997 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 1893997 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6679000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 929000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1365500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1013500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 9987000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 23885500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5496500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 363500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 146000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 29891500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5230500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 470500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 86500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 72500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 5860000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 23885500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 11909500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 5496500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1399500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 363500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 1452000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 146000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 1086000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 45738500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 23885500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 11909500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 5496500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1399500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 363500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 1452000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 146000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 1086000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 45738500 # number of overall MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.966667 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21722.222222 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21763.157895 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21800 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21809.380952 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21770.080460 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71053.191489 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 84458.333333 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 76236.641221 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72700 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73000 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66278.270510 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 72500 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadResp 534 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 287 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 87 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 162 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 231 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 984 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 984 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1019 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
|
|
system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
|
|
system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|