17dbb49294
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup the number of threads before creating interrupt controllers, which confused the constructor in BaseCPU. This changeset adds SMT support to the test configuration infrastructure. --HG-- rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt |
||
|---|---|---|
| .. | ||
| 00.hello | ||
| 00.hello.mp | ||
| 01.hello-2T-smt | ||
| 02.insttest | ||
| 03.learning-gem5 | ||
| 10.mcf | ||
| 20.eio-short | ||
| 30.eio-mp | ||
| 30.eon | ||
| 40.m5threads-test-atomic | ||
| 50.memtest | ||
| 50.vortex | ||
| 60.rubytest | ||
| 70.tgen | ||
| 70.twolf | ||