gem5/src/arch/x86/isa
Gabe Black 1e70401c08 X86: Fix a few bugs with the segment register instructions in real mode.
Fix a few instances where the register form of zext was used where zexti was
intended. Also get rid of the 64 bit only rip relative addressed version since
64 bit and real mode are mutually exclusive.
2009-02-25 10:20:19 -08:00
..
decoder X86: Implement the fence instructions. These are not microcoded. 2009-02-25 10:19:41 -08:00
formats X86: Hook in the M5 pseudo insts. 2009-01-06 23:55:46 -08:00
insts X86: Fix a few bugs with the segment register instructions in real mode. 2009-02-25 10:20:19 -08:00
microops X86: Do a merge for the zero extension microop. 2009-02-25 10:20:10 -08:00
bitfields.isa X86: Add a bitfield to indicate whether or not an REX prefix was present. 2007-07-30 13:17:34 -07:00
includes.isa X86: Implement a basic prefetch instruction. 2009-02-25 10:19:22 -08:00
macroop.isa X86: Autogenerate macroop generateDisassemble function. 2009-01-06 22:55:27 -08:00
main.isa Pull some hard coded base classes out of the isa description. 2007-07-14 17:14:19 -07:00
microasm.isa X86: Make the microcode assembler recognize r8-r15. 2009-02-25 10:17:43 -08:00
operands.isa X86: Add microops for reading/writing debug registers. 2009-02-25 10:20:01 -08:00
outputblock.isa Pull some hard coded base classes out of the isa description. 2007-07-14 17:14:19 -07:00
rom.isa X86: Implement local labels for the ROM that actually refer into the ROM. 2008-10-12 20:44:11 -07:00
specialize.isa X86: Autogenerate macroop generateDisassemble function. 2009-01-06 22:55:27 -08:00