gem5/src/cpu/o3
Gabe Black 19292d3f06 O3: Remove unneeded variable.
--HG--
extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf
2007-11-06 12:51:08 -08:00
..
alpha CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well. 2007-10-02 18:22:36 -07:00
mips Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
sparc CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well. 2007-10-02 18:22:36 -07:00
2bit_local_pred.cc Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
2bit_local_pred.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
base_dyn_inst.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
bpred_unit.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
bpred_unit_impl.hh Make sure the value of PC is actually updated now that the instruction target isn't set explicitly. 2006-12-28 14:29:17 -05:00
btb.cc Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
btb.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
checker_builder.cc CPU: Make the cpuid parameter get set in SE mode as well. 2007-10-02 18:33:57 -07:00
comm.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
commit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
commit.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
commit_impl.hh CPU: Make the cpus check the pc event queues in SE mode. 2007-10-02 18:25:37 -07:00
cpu.cc Rename cycles() function to ticks() 2007-09-28 13:21:52 -04:00
cpu.hh Rename cycles() function to ticks() 2007-09-28 13:21:52 -04:00
cpu_policy.hh Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 2006-06-04 16:07:54 -04:00
decode.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
decode.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
decode_impl.hh Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 2007-04-14 17:13:18 +00:00
dep_graph.hh Miscellaneous minor fixes. 2006-06-16 17:15:18 -04:00
dyn_inst.hh Added an x86 dyninst 2007-03-05 14:55:45 +00:00
fetch.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
fetch.hh Merge zizzer.eecs.umich.edu:/bk/newmem 2007-06-19 18:54:40 -07:00
fetch_impl.hh Merge with head 2007-08-26 21:45:40 -07:00
free_list.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
free_list.hh Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
fu_pool.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
fu_pool.hh params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
FuncUnitConfig.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
FUPool.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
iew.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
iew.hh O3: Remove unneeded variable. 2007-11-06 12:51:08 -08:00
iew_impl.hh O3: Remove unneeded variable. 2007-11-06 12:51:08 -08:00
inst_queue.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
inst_queue.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
inst_queue_impl.hh Rename cycles() function to ticks() 2007-09-28 13:21:52 -04:00
isa_specific.hh Initial changes to get O3 working with SPARC 2006-11-24 22:06:33 -05:00
lsq.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq.hh Change getDeviceAddressRanges to use bool for snoop arg. 2007-05-21 23:36:09 -07:00
lsq_impl.hh Merge with head 2007-08-26 21:45:40 -07:00
lsq_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
lsq_unit.hh Make CPU models use new LoadLockedReq/StoreCondReq commands. 2007-06-30 20:35:42 -07:00
lsq_unit_impl.hh Merge with head 2007-08-26 21:45:40 -07:00
mem_dep_unit.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
mem_dep_unit.hh Initialize mem dep unit properly. 2006-11-07 13:53:06 -05:00
mem_dep_unit_impl.hh Handle status bits a little better, as well as non-speculative instructions. 2007-03-23 11:40:53 -04:00
O3Checker.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
O3CPU.py Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
params.hh Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. 2006-10-31 14:33:56 -05:00
ras.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
ras.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
regfile.hh Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
rename.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rename.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
rename_impl.hh X86: Put in the foundation for x87 stack based fp registers. 2007-09-19 18:26:42 -07:00
rename_map.cc Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
rename_map.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
rob.cc now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory 2006-06-30 20:49:31 -04:00
rob.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
rob_impl.hh Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. 2007-04-04 15:38:59 -04:00
sat_counter.cc Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
sat_counter.hh Merge ktlim@zizzer:/bk/newmem 2006-06-02 18:19:50 -04:00
SConscript Traceflags: Add SCons function to created a traceflag instead of having one file with them all. 2007-10-31 01:21:54 -04:00
SConsopts Rework the way SCons recurses into subdirectories, making it 2007-03-10 23:00:54 -08:00
scoreboard.cc Make the floating point zero register special handling only apply for ALPHA. 2007-04-22 17:50:43 +00:00
scoreboard.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
store_set.cc Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses. 2006-06-05 18:14:39 -04:00
store_set.hh Cleaned up include files and got rid of many using directives in header files. 2006-08-15 05:07:15 -04:00
thread_context.hh Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 2007-08-26 20:24:18 -07:00
thread_context_impl.hh X86: Put in the foundation for x87 stack based fp registers. 2007-09-19 18:26:42 -07:00
thread_state.hh Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. 2006-10-31 14:33:56 -05:00
tournament_pred.cc Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
tournament_pred.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00