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alpha
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CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well.
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2007-10-02 18:22:36 -07:00 |
mips
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Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
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2007-08-26 20:24:18 -07:00 |
sparc
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CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well.
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2007-10-02 18:22:36 -07:00 |
2bit_local_pred.cc
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Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
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2006-06-04 16:07:54 -04:00 |
2bit_local_pred.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
base_dyn_inst.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
bpred_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
bpred_unit.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
bpred_unit_impl.hh
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Make sure the value of PC is actually updated now that the instruction target isn't set explicitly.
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2006-12-28 14:29:17 -05:00 |
btb.cc
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
btb.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
checker_builder.cc
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CPU: Make the cpuid parameter get set in SE mode as well.
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2007-10-02 18:33:57 -07:00 |
comm.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
commit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
commit.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
commit_impl.hh
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CPU: Make the cpus check the pc event queues in SE mode.
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2007-10-02 18:25:37 -07:00 |
cpu.cc
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Rename cycles() function to ticks()
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2007-09-28 13:21:52 -04:00 |
cpu.hh
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Rename cycles() function to ticks()
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2007-09-28 13:21:52 -04:00 |
cpu_policy.hh
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Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
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2006-06-04 16:07:54 -04:00 |
decode.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
decode.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
decode_impl.hh
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Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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2007-04-14 17:13:18 +00:00 |
dep_graph.hh
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Miscellaneous minor fixes.
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2006-06-16 17:15:18 -04:00 |
dyn_inst.hh
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Added an x86 dyninst
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2007-03-05 14:55:45 +00:00 |
fetch.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
fetch.hh
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Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-06-19 18:54:40 -07:00 |
fetch_impl.hh
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Merge with head
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2007-08-26 21:45:40 -07:00 |
free_list.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
free_list.hh
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
fu_pool.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
fu_pool.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
FuncUnitConfig.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
FUPool.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
iew.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
iew.hh
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O3: Remove unneeded variable.
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2007-11-06 12:51:08 -08:00 |
iew_impl.hh
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O3: Remove unneeded variable.
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2007-11-06 12:51:08 -08:00 |
inst_queue.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
inst_queue.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
inst_queue_impl.hh
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Rename cycles() function to ticks()
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2007-09-28 13:21:52 -04:00 |
isa_specific.hh
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Initial changes to get O3 working with SPARC
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2006-11-24 22:06:33 -05:00 |
lsq.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
lsq.hh
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Change getDeviceAddressRanges to use bool for snoop arg.
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2007-05-21 23:36:09 -07:00 |
lsq_impl.hh
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Merge with head
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2007-08-26 21:45:40 -07:00 |
lsq_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
lsq_unit.hh
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Make CPU models use new LoadLockedReq/StoreCondReq commands.
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2007-06-30 20:35:42 -07:00 |
lsq_unit_impl.hh
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Merge with head
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2007-08-26 21:45:40 -07:00 |
mem_dep_unit.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
mem_dep_unit.hh
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Initialize mem dep unit properly.
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2006-11-07 13:53:06 -05:00 |
mem_dep_unit_impl.hh
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Handle status bits a little better, as well as non-speculative instructions.
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2007-03-23 11:40:53 -04:00 |
O3Checker.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
O3CPU.py
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Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
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2007-08-26 20:24:18 -07:00 |
params.hh
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Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
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2006-10-31 14:33:56 -05:00 |
ras.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
ras.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
regfile.hh
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
rename.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
rename.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
rename_impl.hh
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X86: Put in the foundation for x87 stack based fp registers.
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2007-09-19 18:26:42 -07:00 |
rename_map.cc
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
rename_map.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
rob.cc
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now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
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2006-06-30 20:49:31 -04:00 |
rob.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
rob_impl.hh
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Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.
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2007-04-04 15:38:59 -04:00 |
sat_counter.cc
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
sat_counter.hh
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Merge ktlim@zizzer:/bk/newmem
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2006-06-02 18:19:50 -04:00 |
SConscript
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Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
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2007-10-31 01:21:54 -04:00 |
SConsopts
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Rework the way SCons recurses into subdirectories, making it
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2007-03-10 23:00:54 -08:00 |
scoreboard.cc
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Make the floating point zero register special handling only apply for ALPHA.
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2007-04-22 17:50:43 +00:00 |
scoreboard.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
store_set.cc
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Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses.
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2006-06-05 18:14:39 -04:00 |
store_set.hh
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Cleaned up include files and got rid of many using directives in header files.
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2006-08-15 05:07:15 -04:00 |
thread_context.hh
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Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
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2007-08-26 20:24:18 -07:00 |
thread_context_impl.hh
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X86: Put in the foundation for x87 stack based fp registers.
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2007-09-19 18:26:42 -07:00 |
thread_state.hh
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Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
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2006-10-31 14:33:56 -05:00 |
tournament_pred.cc
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Merge ktlim@zamp:./local/clean/o3-merge/m5
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2006-09-30 23:43:23 -04:00 |
tournament_pred.hh
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Merge ktlim@zamp:./local/clean/o3-merge/m5
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2006-09-30 23:43:23 -04:00 |