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gem5/tests/configs
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Andreas Hansson c4898b15bc mem: Add DDR3 and LPDDR2 DRAM controller configurations 
This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
2013-01-31 07:49:14 -05:00
..
alpha_generic.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
arm_generic.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
base_config.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
inorder-timing.py mem: Add DDR3 and LPDDR2 DRAM controller configurations 2013-01-31 07:49:14 -05:00
memtest-ruby.py Configs: Set the memtest clock to a reasonable value 2012-10-15 08:09:57 -04:00
memtest.py config: Unify caches used in regressions and adjust L2 MSHRs 2012-10-30 07:44:08 -04:00
o3-timing-checker.py mem: Add DDR3 and LPDDR2 DRAM controller configurations 2013-01-31 07:49:14 -05:00
o3-timing-mp-ruby.py tests: Always specify memory mode in every test system. 2013-01-07 13:05:33 -05:00
o3-timing-mp.py mem: Add DDR3 and LPDDR2 DRAM controller configurations 2013-01-31 07:49:14 -05:00
o3-timing-ruby.py tests: Always specify memory mode in every test system. 2013-01-07 13:05:33 -05:00
o3-timing.py mem: Add DDR3 and LPDDR2 DRAM controller configurations 2013-01-31 07:49:14 -05:00
pc-o3-timing.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
pc-simple-atomic.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
pc-simple-timing-ruby.py Regression: Fix topologies path in failing pc-simple-timing-ruby 2012-07-21 17:24:01 -04:00
pc-simple-timing.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-o3-checker.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-o3-dual.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-o3.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-simple-atomic-dual.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-simple-atomic.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-simple-timing-dual.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-simple-timing.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
realview-switcheroo-atomic.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
realview-switcheroo-full.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
realview-switcheroo-o3.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
realview-switcheroo-timing.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
rubytest-ruby.py regress: ruby stat additions and config changes 2012-07-10 22:51:55 -07:00
simple-atomic-dummychecker.py Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
simple-atomic-mp-ruby.py regress: ruby stat additions and config changes 2012-07-10 22:51:55 -07:00
simple-atomic-mp.py stats: Update stats for fixed simple-atomic-mp config 2012-10-31 08:39:45 -04:00
simple-atomic.py Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
simple-timing-mp-ruby.py regress: ruby stat additions and config changes 2012-07-10 22:51:55 -07:00
simple-timing-mp.py config: Unify caches used in regressions and adjust L2 MSHRs 2012-10-30 07:44:08 -04:00
simple-timing-ruby.py regress: ruby stat additions and config changes 2012-07-10 22:51:55 -07:00
simple-timing.py tests: Always specify memory mode in every test system. 2013-01-07 13:05:33 -05:00
switcheroo.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
t1000-simple-atomic.py Fix the SPARC fs regression by adding a call to createInterruptController. 2012-03-08 02:10:03 -08:00
tgen-simple-dram.py mem: Add DDR3 and LPDDR2 DRAM controller configurations 2013-01-31 07:49:14 -05:00
tgen-simple-mem.py cpu: Add support for protobuf input for the trace generator 2013-01-07 13:05:37 -05:00
tsunami-inorder.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
tsunami-o3-dual.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
tsunami-o3.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
tsunami-simple-atomic-dual.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
tsunami-simple-atomic.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
tsunami-simple-timing-dual.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
tsunami-simple-timing.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00
tsunami-switcheroo-full.py tests: Add CPU switching tests 2013-01-07 13:05:52 -05:00
twosys-tsunami-simple-atomic.py config: Do not use hardcoded physmem in fs script 2013-01-07 13:05:38 -05:00
x86_generic.py tests: Create base classes to encapsulate common test configurations 2013-01-07 13:05:33 -05:00