gem5/src/cpu/simple
Gabe Black 10c2e37f60 Syscall: Make the syscall function available in both SE and FS modes.
In FS mode the syscall function will panic, but the interface will be
consistent and code which calls syscall can be compiled in. This will allow,
for instance, instructions that use syscall to be built unconditionally but
then not returned by the decoder.
2011-09-19 02:46:48 -07:00
..
atomic.cc ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
atomic.hh ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
AtomicSimpleCPU.py Config: Keep track of uncached and cached ports separately. 2011-02-03 20:23:00 -08:00
base.cc Decode: Pull instruction decoding out of the StaticInst class into its own. 2011-09-09 02:30:01 -07:00
base.hh Syscall: Make the syscall function available in both SE and FS modes. 2011-09-19 02:46:48 -07:00
BaseSimpleCPU.py params: Convert the CPU objects to use the auto generated param structs. 2008-08-11 12:22:16 -07:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
timing.cc Translation: Use a pointer type as the template argument. 2011-08-07 09:21:48 -07:00
timing.hh ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
TimingSimpleCPU.py Config: Keep track of uncached and cached ports separately. 2011-02-03 20:23:00 -08:00