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gem5/src/cpu/inorder
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Korey Sewell 0a74246fb9 inorder: InstSeqNum bug 
Because int and not InstSeqNum was used in a couple of places, you can
overflow the int type and thus get wierd bugs when the sequence number
is negative (or some wierd value)
2011-02-23 16:35:18 -05:00
..
resources inorder: InstSeqNum bug 2011-02-23 16:35:18 -05:00
comm.hh inorder: stage width as a python parameter 2011-02-04 00:08:18 -05:00
cpu.cc inorder: update graduation unit 2011-02-18 14:30:05 -05:00
cpu.hh inorder: cleanup in destructors 2011-02-18 14:29:26 -05:00
first_stage.cc inorder: utilize cached skeds in pipeline 2011-02-12 10:14:45 -05:00
first_stage.hh inorder: pipe. stage inst. buffering 2011-02-04 00:08:16 -05:00
inorder_cpu_builder.cc inorder-alpha-fs: edit inorder model to compile FS mode 2009-09-15 01:44:48 -04:00
inorder_dyn_inst.cc inorder: dyn inst initialization 2011-02-23 16:35:04 -05:00
inorder_dyn_inst.hh inorder: dyn inst initialization 2011-02-23 16:35:04 -05:00
inorder_trace.cc Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
inorder_trace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
InOrderCPU.py inorder: add a fetch buffer to fetch unit 2011-02-04 00:08:22 -05:00
InOrderTrace.py InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
params.hh Remove unused functions/comments cluttering up the code. 2009-03-04 13:17:08 -05:00
pipeline_stage.cc inorder: cleanup in destructors 2011-02-18 14:29:26 -05:00
pipeline_stage.hh inorder: cleanup in destructors 2011-02-18 14:29:26 -05:00
pipeline_traits.5stage.cc InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.5stage.hh InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.cc InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.hh InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.smt2.cc InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.9stage.smt2.hh InOrder: Import new inorder CPU model from MIPS. 2009-02-10 15:49:29 -08:00
pipeline_traits.hh inorder: update default thread size(=1) 2011-02-18 14:29:44 -05:00
reg_dep_map.cc inorder: cleanup in destructors 2011-02-18 14:29:26 -05:00
reg_dep_map.hh inorder: cleanup in destructors 2011-02-18 14:29:26 -05:00
resource.cc inorder: add names and slot #s to res. dprints 2011-02-18 14:31:31 -05:00
resource.hh inorder: add names and slot #s to res. dprints 2011-02-18 14:31:31 -05:00
resource_pool.9stage.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
resource_pool.cc inorder: update max. resource bandwidths 2011-02-18 14:29:31 -05:00
resource_pool.hh inorder: utilize cached skeds in pipeline 2011-02-12 10:14:45 -05:00
resource_sked.cc inorder: utilize cached skeds in pipeline 2011-02-12 10:14:45 -05:00
resource_sked.hh inorder: define iterator for resource schedules 2011-02-12 10:14:43 -05:00
SConscript inorder: clean up the old way of inst. scheduling 2011-02-12 10:14:48 -05:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
thread_context.cc ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
thread_context.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00
thread_state.cc inorder-alpha-fs: edit inorder model to compile FS mode 2009-09-15 01:44:48 -04:00
thread_state.hh ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. 2010-10-31 00:07:20 -07:00