Matt Horsnell 031f396c71 ARM: Fix RFE macrop. ... This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.		2011-03-17 19:20:19 -05:00
..
decoder	ARM: Add support for M5 ops in the ARM ISA	2010-11-08 13:58:24 -06:00
formats	ARM: Do something for ISB, DSB, DMB	2011-02-23 15:10:49 -06:00
insts	ARM: Fix RFE macrop.	2011-03-17 19:20:19 -05:00
templates	ARM: Fix RFE macrop.	2011-03-17 19:20:19 -05:00
bitfields.isa	ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.	2010-06-02 12:58:07 -05:00
copyright.txt	ARM: Remove IsControl from operands that don't imply control transfers.	2010-06-02 12:57:59 -05:00
includes.isa	ARM: Add support for M5 ops in the ARM ISA	2010-11-08 13:58:24 -06:00
main.isa	ARM: Define the load instructions from outside the decoder.	2010-06-02 12:58:01 -05:00
operands.isa	ARM: Rename registers used as temporary state by microops.	2011-03-17 19:20:19 -05:00