Commit graph

6 commits

Author SHA1 Message Date
Andreas Hansson
fce3433b2e stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
2013-01-31 07:49:16 -05:00
Andreas Hansson
1da209140c cpu: Add support for protobuf input for the trace generator
This patch adds support for reading input traces encoded using
protobuf according to what is done in the CommMonitor.

A follow-up patch adds a Python script that can be used to convert the
previously used ASCII traces to protobuf equivalents. The appropriate
regression input is updated as part of this patch.
2013-01-07 13:05:37 -05:00
Andreas Hansson
79b4477302 stats: Update DRAM regression stats to match new config
This patch updates the regression stats to reflect the change in the
traffic gen configuration.
2013-01-07 13:05:36 -05:00
Andreas Hansson
7216681561 config: Reduce DRAM controller regression traffic rate
This patch changes the traffic generator period such that it does not
completely saturate the DRAM controller and create an ever-growing
backlog in the queued port.

A separate patch updates the stats.
2013-01-07 13:05:36 -05:00
Andreas Hansson
6427342318 SimpleDRAM: A basic SimpleDRAM regression
--HG--
rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py
rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg
rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 11:48:14 -04:00
Andreas Hansson
efea870fce TrafficGen: Add a basic traffic generator regression
This patch adds a basic regression for the traffic generator. The
regression also serves as an example of the file formats used. More
complex regressions that make use of a DRAM controller model will
follow shortly.
2012-09-21 11:48:11 -04:00