src/mem/cache/cache_impl.hh:
Fix a error case by putting a panic in.
Make sure to propogate sendFunctional calls with functional not atomic.
--HG--
extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
src/mem/cache/cache_impl.hh:
Make sure to pop the list. Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
Add an assert as sanity check in case .full() stops working again.
--HG--
extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.
src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
add the periodicity of checkpointing back into the code.
to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.
--HG--
extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
And small other tweaks to snooping coherence.
src/mem/cache/base_cache.hh:
Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
Add the function to create an atomic response to a given request
--HG--
extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache
src/mem/bus.cc:
Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
Support range changes for snoops
Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
Only access the cache if it wasn't satisfied by cache->cache transfer
Handle snoop phases (detect block, then snoop)
Fix functional access to work properly (still need to fix snoop path for functional accesses)
--HG--
extra : convert_revision : 4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
-Basically removed the ASID from places it is no longer needed due to PageTable
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
Remove asid where it wasn't neccesary anymore due to Page Table
--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))
src/cpu/simple/timing.cc:
Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
Handle marking MSHR's in service
Add support for getting CSHR's
src/mem/cache/base_cache.hh:
Make these functions visible at the base cache level
src/mem/cache/cache.hh:
make the functions virtual
src/mem/cache/cache_impl.hh:
Rename the function to make sense
src/mem/packet.hh:
Accidentally clearing the needsResponse field when sending a response back.
--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
Need to clean up a bunch of flags/hacks in the code. Then onto Timming mode.
Functional accesses also work properly, although not exactly how we wanted them. I'll need to clean that up as well.
src/cpu/simple/atomic.cc:
Atomic CPU needs to set thread context so stats work in cache. Temporarily just use CPU=0 ThreadID=0
src/mem/cache/cache_impl.hh:
Need to return success/failure properly still
Physical memory object doesn't assert SATISFIED anymore, need to remove that flag
src/mem/cache/tags/lru.cc:
Doesn't work if the REQ doesn't set it's ASID. Temporary fix use 0 always
--HG--
extra : convert_revision : d06a39684af593db699b64df9a29f80c61d8d050
Compile and initialization work, still working on functionality.
src/mem/cache/base_cache.cc:
Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects.
Also, all packets have to have data or the delete fails.
src/mem/cache/cache.hh:
Fix function prototypes so overloading works
src/mem/cache/cache_impl.hh:
fix functions to match virtual base class
src/mem/cache/miss/miss_queue.cc:
Packets havve to have data, or delete fails
src/python/m5/objects/BaseCache.py:
Update for newmem
--HG--
extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb
This now compiles.
src/mem/cache/base_cache.cc:
Fix getPort function that changed
src/mem/cache/base_cache.hh:
Fix get port function, provide default implementations of virtual functions in the base class
src/mem/cache/cache.hh:
Fix virtual function declerations
src/mem/cache/cache_builder.cc:
Fix params
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
Properly allocate data in packet
--HG--
extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48
Some implementation details were left blank still, need to fill them in.
src/SConscript:
Reorder build to compile all files first
src/mem/cache/cache.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
More changesets pulled, now compiles everything in /miss directory and in the root directory
src/mem/packet.hh:
Add some more support, need to clean some of it out once everything is working
--HG--
extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800
