arch/alpha/ev5.cc:
actually implement the cycle count register
arch/alpha/isa_desc:
the rpcc instruction really just reads the cycle count
register
--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
arch/alpha/ev5.cc:
Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
(Very slightly).
arch/alpha/isa_desc:
Upper half of rpcc result comes from value written
to IPR_CC, not actual cycle counter.
--HG--
extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125
arch/alpha/isa_desc:
Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
Add copy functions to SimpleCPU as well
--HG--
extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d
arch/alpha/osfpal.cc:
Add a string for copypal.
arch/alpha/osfpal.hh:
Add a code for copypal.
cpu/static_inst.hh:
Add an IsCopy flag.
--HG--
extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f
it actually do something on FullCPU. Still disabled, as it
causes detailed-boot to hang when you turn it on.
arch/alpha/isa_desc:
Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
Changed prefetch() return type from Fault to void.
--HG--
extra : convert_revision : c7cb42682bfea6af117c87d4dfdb06176b6fe6b7
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
same thing for simple cpu's.
--HG--
extra : convert_revision : aac9f91742866fb26f8cace622f9b88454a69662
util/tracediff:
Quote simulator args so args with spaces get handled correctly.
--HG--
extra : convert_revision : b48677bc712be17e6e50ca35680e757ba9364692
so add some states to indicate that the dma read/write
hasn't issued yet, and add some support to reissue the
request when the interface becomes unblocked.
--HG--
extra : convert_revision : 448695a8eb2e9f98554769f3165df1f796adf44a
(very painful) bus reset from occuring
base/loader/elf_object.cc:
Fixed to allow proper loading of local symbols
--HG--
extra : convert_revision : 5c9a1f4d7b5748a1c8cabdfd67763c21f988f8fd
and a physical memory address for DMA
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
Changed registers to array and added mapping function to translate between
PCI bus space and physical address space
--HG--
extra : convert_revision : e9dc4de4e7effe8e8e2365298843d6f767b5a289
sim/sim_object.cc:
serialize objects in the reverse order of their creation.
This causes a SimObject that is dependent on another
to be serialized first. For example, the ethernet device
writes back some data to physical memory while serializing,
so this will cause the physical memory to be serialized
after that, preserving the data written back.
--HG--
extra : convert_revision : f9a37b63ce777df1cfecefa80f94f8fc69e42448
of faking it. Renamed stuff to follow our style. Lots of
general cleanup.
dev/etherpkt.hh:
fix up includes
--HG--
extra : convert_revision : fb3a21466cdae00f8747d6e3027c9f2c63569c48
are present
dev/tsunami_cchip.cc:
Only need to interrupt processors that are there
Move RTC interrupt code into a function
dev/tsunami_cchip.hh:
Make a RTC interrupt function, move variables out of public scope
dev/tsunami_io.cc:
Make a call to the RTC interrupt routine instead
--HG--
extra : convert_revision : 88113664d0e54a7dddc00ec11ff9b9d088232b31
make it so that pio devices must respond with some delay.
dev/io_device.cc:
don't forget to include dma_interface.hh so we could use it.
dev/io_device.hh:
the generic BusInterface isn't enough for doing DMA
we need the actual DMAInterface
--HG--
extra : convert_revision : 70298d33c8520a3f4ad11aa600825a8cec7e44bf
dev/etherdump.cc:
now that init is automatically called by the framework, don't
init twice.
--HG--
extra : convert_revision : 16dcdef67aa193ed71ff546e7b255d60f39bf13d
dev/tsunami_cchip.cc:
Add support for IPI, making changes to read/write to MISC register
Particularly the IPREQ, IPINTR, and ITINTR subfields
dev/tsunami_cchip.hh:
Make an array to keep track of the number of outstanding IPI's,
Extend RTC to interrupt all processors, not just cpu0
dev/tsunami_io.cc:
Extend RTC to interrupt all present proccessors, not just cpu0
--HG--
extra : convert_revision : 0715cbf0abb06002c0fb0b05ef369304cdf75001
physical addressing. This has the uncacheable bit as bit 40 as opposed
to bit 39. Additionally, we now support (at least superficially) a 44-bit
physical address. To deal with superpage access in this scheme, any super
page access with either bit 39 or 40 set is sign extended.
--HG--
extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab
tlb index calls that are called from ExecContext::readIpr
arch/alpha/ev5.cc:
Fix misspeculation bugs for misspeculated IPR accesses
--HG--
extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7
