Commit graph

11861 commits

Author SHA1 Message Date
Andreas Sandberg
cd098a7e84 dev: Add a simple DMA engine that can be used by devices
Add a simple DMA engine that sits behind a FIFO. This engine can be
used by devices that need to read large amounts of data (e.g., display
controllers). Most aspects of the controller, such as FIFO size,
maximum number of in-flight accesses, and maximum request sizes can be
configured.

The DMA copies blocks of data into its FIFO. Transfers are initiated
with a call to startFill() command that takes a start address and a
size. Advanced users can create a derived class that overrides the
onEndOfBlock() callback that is triggered when the last request to a
block has been issued. At this point, the DMA engine is ready to start
fetching a new block of data, potentially from a different address
range.

The DMA engine stops issuing new requests while it is draining. Care
must be taken to ensure that devices that are fed by a DMA engine are
suspended while the system is draining to avoid buffer underruns.
2015-08-07 09:59:23 +01:00
Andreas Sandberg
f7ff27afe8 sim: Split ClockedObject to make it usable to non-SimObjects
Split ClockedObject into two classes: Clocked that provides the basic
clock functionality, and ClockedObject that inherits from Clocked and
SimObject to provide the functionality of the old ClockedObject.
2015-08-07 09:59:22 +01:00
Andreas Sandberg
9b2426ecfc base: Rewrite the CircleBuf to fix bugs and add serialization
The CircleBuf class has at least one bug causing it to overwrite the
wrong elements when wrapping. The current code has a lot of unused
functionality and duplicated code. This changeset replaces the old
implementation with a new version that supports serialization and
arbitrary types in the buffer (not just char).
2015-08-07 09:59:19 +01:00
Andreas Sandberg
39d8034475 dev, x86: Fix serialization bug in the i8042 device
The i8042 device drops the contents of a PS2 device's buffer when
serializing, which results in corrupted PS2 state when continuing
simulation after a checkpoint. This changeset fixes this bug and
transitions the i8042 model to use the new serialization API that
requires the serialize() method to be const.
2015-08-07 09:59:15 +01:00
Andreas Sandberg
af6b51925c dev: Make serialization in Sinic constant
This changeset transitions the Sinic device to the new serialization
framework that requires the serialization method to be constant.
2015-08-07 09:59:14 +01:00
Andreas Sandberg
53e777d683 base: Declare a type for context IDs
Context IDs used to be declared as ad hoc (usually as int). This
changeset introduces a typedef for ContextIDs and a constant for
invalid context IDs.
2015-08-07 09:59:13 +01:00
Andreas Sandberg
3e26756f1d base: Use constexpr in Cycles
Declare the constructor and all of the operators that don't change the
state of a Cycles instance as constexpr. This makes it possible to use
Cycles as a static constant and allows the compiler to evaulate simple
expressions at compile time. An unfortunate side-effect of this is
that we cannot use assertions since C++11 doesn't support them in
constexpr functions. As a workaround, we throw an invalid_argument
exception when the assert would have triggered. A nice side-effect of
this is that the compiler will evaluate the "assertion" at compile
time when an expression involving Cycles can be statically evaluated.
2015-08-07 09:59:12 +01:00
Andreas Hansson
83a668ad25 mem: Remove extraneous acquire/release flags and attributes
This patch removes the extraneous flags and attributes from the
request and packet, and simply leaves the new commands. The change
introduced when adding acquire/release breaks all compatibility with
existing traces, and there is really no need for any new flags and
attributes. The commands should be sufficient.

This patch fixes packet tracing (urgent), and also removes the
unnecessary complexity.
2015-08-07 04:55:38 -04:00
Andreas Sandberg
07815a3338 sim: Fixup comments and constness in draining infrastructure
Fix comments that got outdated by the draining rewrite. Also fixup
constness for methods in the querying drain state in the DrainManager.
2015-08-05 10:27:11 +01:00
Andreas Sandberg
0194e6eb2d mem: Fixup incorrect include guards
--HG--
extra : rebase_source : 9dba84eaf9c734a114ecd0940e1d505303644064
2015-08-05 10:12:12 +01:00
Andreas Hansson
d540ba0325 util: Enable DRAM sweep to print power and efficiency
This patch enhances the functionality of the DRAM sweep script to not
only plot the bandwidth utilisation, but also total power and power
efficiency. To do so, a command-line switch is added, and a bit more
data extracted from the stats.
2015-08-05 04:36:31 -04:00
Andreas Hansson
646994e599 stats: Reflect current behaviour
Not sure what went wrong in the pushing of the Ruby patches, but
somehow these regressions are not updated.
2015-08-05 04:36:29 -04:00
Andreas Sandberg
7c904d9d3f sim: Initialize Drainable::_drainState to the system's state
It is sometimes desirable to be able to instantiate Drainable objects
when the simulator isn't in the Running state. Currently, we always
initialize Drainable objects to the Running state. However, this
confuses many of the sanity checks in the base class since objects
aren't expected to be in the Running state if the system is in the
Draining or Drained state.

Instead of always initializing the state variable in Drainable to
DrainState::Running, initialize it to the state the DrainManager is
in.

Note: This means an object can be created in the Draining/Drained
state without first calling drain().
2015-08-04 10:31:37 +01:00
Andreas Sandberg
1a7802598b stats: Update stats for tgen to reflect CommMonitor changes
The name of the stack distance stats changed slightly when the stack
distance calculator was redesigned as a probe. Update the reference
stats to reflect this.
2015-08-04 10:29:13 +01:00
Andreas Sandberg
a3f49f60c7 mem: Move trace functionality from the CommMonitor to a probe
This changeset moves the access trace functionality from the
CommMonitor into a separate probe. The probe can be hooked up to any
component that exports probe points of the type ProbePoints::Packet.

This patch moves the dependency on Google's Protocol Buffers library
from the CommMonitor to the MemTraceProbe, which means that the
CommMonitor (including stack distance profiling) no long depends on
it.
2015-08-04 10:29:13 +01:00
Andreas Sandberg
022e69e6de mem: Redesign the stack distance calculator as a probe
This changeset removes the stack distance calculator hooks from the
CommMonitor class and implements a stack distance calculator as a
memory system probe instead. The probe can be hooked up to any
component that exports probe points of the type ProbePoints::Packet.
2015-08-04 10:29:13 +01:00
Andreas Sandberg
feded87fc9 mem: Add probe support to the CommMonitor
This changeset adds a standardized probe point type to monitor packets
in the memory system and adds two probe points to the CommMonitor
class. These probe points enable monitoring of successfully delivered
requests and successfully delivered responses.

Memory system probe listeners should use the BaseMemProbe base class
to provide a unified configuration interface and reuse listener
registration code. Unlike the ProbeListenerObject class, the
BaseMemProbe allows objects to be wired to multiple ProbeManager
instances as long as they use the same probe point name.
2015-08-04 10:29:13 +01:00
Matthias Jung
8723b08dbf misc: Coupling gem5 with SystemC TLM2.0
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.

Compared to the original patch a TLM memory manager was added. Furthermore, the
transaction object was removed and for each TLM payload a PacketPointer that
points to the original gem5 packet is added as an TLM extension.  For event
handling single events are now created.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-08-03 23:08:40 -05:00
Timothy Jones
c375870abd sim: function for testing for auto deletion
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-08-03 23:08:40 -05:00
Timothy Jones
96091f358b uby: Fix checkpointing and restore
There are 2 problems with the existing checkpoint and restore code in ruby.
The first is that when the event queue is altered by ruby during serialization,
some events that are currently scheduled cannot be found (e.g. the event to
stop simulation that always lives on the queue), causing a panic.
The second is that ruby is sometimes serialized after the memory system,
meaning that the dirty data in its cache is flushed back to memory too late
and so isn't included in the checkpoint.

These are fixed by implementing memory writeback in ruby, using the same
technique of hijacking the event queue, but first descheduling all events that
are currently on it.  They are saved, along with their scheduled time, so that
the event queue can be faithfully reconstructed after writeback has finished.
Events with the AutoDelete flag set will delete themselves when they
are descheduled, causing an error when attempting to schedule them again.
This is fixed by simply not recording them when taking them off the queue.

Writeback is still implemented using flushing, so the cache recorder object,
that is created to generate the trace and manage flushing, is kept
around and used during serialization to write the trace to disk.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-08-03 23:08:40 -05:00
Nilay Vaish
676ae57827 ruby: mesi three level: multiple corrections to the protocol
1. Eliminate state NP in L0 and L1 Caches:  The two states 'NP' and 'I' both
mean that the cache block is not present in the cache.  'I' also means that the
cache entry has been allocated.  This causes problems when we do not correctly
initialize the cache entry when it is re-used.  Hence, this patch eliminates
the state NP altogether.  Everytime a new block comes into the cache, a cache
entry is allocated.  Everytime a block leaves, the corresponding entry is
deallocated.

2. Separate transient state for instruction fetches: purely for accouting
purposes.

3. Drop state IS_I in L1 Cache and the message type STALE_DATA: when
invalidation is received for a block in IS, the block used to be moved to IS_I.
This meant that the data that would arrive in future would be used but not
stored since the controller lost the permissions after gaining them.  This
state is being dropped and now invalidation messages would not processed till
the data has arrived.  This also means that STALE_DATA type is not longer
required.
2015-08-03 22:44:29 -05:00
Nilay Vaish
9bf3b8828a ruby: mesi two,three level: copy data only when dirty
The level 2 controller has a bug. In one particular action, the data block was
copied from a message irrespective whether the block is dirty or not.  In cases
when L1 sends no data, the data value copied was incorrect.
2015-08-03 22:44:28 -05:00
Nilay Vaish
3d782f8df7 ruby: correctly number the sequencer in MESI_Three_Level.py 2015-08-03 22:44:27 -05:00
Brad Beckmann
03f2b8c23d ruby: removed invalid assert in message comparitor
It is perfectly valid to compare the same message and the greater than
operator should work correctly.
2015-08-01 12:59:47 -04:00
Brad Beckmann
6b52f828cc ruby: improved stall and wait debugging
Added dprintfs and asserts for identifying stall and wait bugs.
2015-07-20 09:15:18 -05:00
Brad Beckmann
848861a17d slicc: fix error in conflicing symbol declaration 2015-07-20 09:15:18 -05:00
Brad Beckmann
8a54adc2a5 slicc: enable overloading in functions not in classes
For many years the slicc symbol table has supported overloaded functions in
external classes.  This patch extends that support to functions that are not
part of classes (a.k.a. no parent).  For example, this support allows slicc
to understand that mapAddressToRange is overloaded and the NodeID is an
optional parameter.
2015-07-20 09:15:18 -05:00
David Hashe
0d00cbc97b ruby: change router pipeline stages to 2
This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.
2015-07-20 09:15:18 -05:00
David Hashe
8b32dad4d8 ruby: change advance_stage for flit_d
Sets m_stage.second to the second parameter of the function.
Then, for every place where advance_stage is called, adds
a cycle to the argument being passed.
2015-07-20 09:15:18 -05:00
Brad Beckmann
f9fa242f42 slicc: improved stalling support in protocols
Adds features to allow protocols to reschedule controllers when conditionally
stalling within inport logic or actions.  Also insures that resource and
protocol stalls are re-evaluated the next cycle.
2015-07-20 09:15:18 -05:00
David Hashe
c4ffd4989c ruby: expose access permission to replacement policies
This patch adds support that allows the replacement policy to identify each
cache block's access permission.  This information can be useful when making
replacement decisions.
2015-07-20 09:15:18 -05:00
David Hashe
967cfa939a ruby: adds size and empty apis to the msg buffer stallmap 2015-07-20 09:15:18 -05:00
David Hashe
21aa5734a0 ruby: fix deadlock bug in banked array resource checks
The Ruby banked array resource checks (initiated from SLICC) did a check and
allocate at the same time. If a transition needs more than one resource, then
it might check/allocate resource #1, then fail to get resource #2. Another
transition might then try to get the same resources, but in reverse order.
Deadlock.

This patch separates resource checking and resource reservation into two
steps to avoid deadlock.
2015-07-20 09:15:18 -05:00
David Hashe
63a9f10de8 ruby: Fix for stallAndWait bug
It was previously possible for a stalled message to be reordered after an
incomming message. This patch ensures that any stalled message stays in its
original request order.
2015-07-20 09:15:18 -05:00
David Hashe
fbb220b4ae config: add base class for ruby controllers
The CntrlBase python class handles configuration parameters such as running
counts of controllers and sequencers.
2015-07-20 09:15:18 -05:00
David Hashe
6511ab4654 mem: add request types for acquire and release
Add support for acquire and release requests.  These synchronization operations
are commonly supported by several modern instruction sets.
2015-07-20 09:15:18 -05:00
David Hashe
7e9562013b ruby: allocate a block in CacheMemory without updating LRU state 2015-07-20 09:15:18 -05:00
David Hashe
7e00772bda ruby: speed up function used for cache walks
This patch adds a few helpful functions that allow .sm files to directly
invalidate all cache blocks using a trigger queue rather than rely on each
individual cache block to be invalidated via requests from the mandatory
queue.
2015-07-20 09:15:18 -05:00
David Hashe
3454a4a36e slicc: support for arbitrary DPRINTF flags (not just RubySlicc)
This patch allows DPRINTFs to be used in SLICC state machines similar to how
they are used by the rest of gem5.  Previously all DPRINTFs in the .sm files
had to use the RubySlicc flag.
2015-07-20 09:15:18 -05:00
David Hashe
9324239922 slicc: support for local variable declarations in action blocks 2015-07-20 09:15:18 -05:00
David Hashe
1850ed410f ruby: initialize replacement policies with their own simobjs
this is in preparation for other replacement policies that take additional
parameters.
2015-07-20 09:15:18 -05:00
David Hashe
74ca89f8b7 ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.
2015-07-20 09:15:18 -05:00
David Hashe
536e3664e4 slicc: support for multiple cache entry types in the same state machine
To have multiple Entry types (e.g., a cache Entry type and
a directory Entry type), just declare one of them as a secondary
type by using the pair 'main="false"', e.g.:

  structure(DirEntry, desc="...", interface="AbstractCacheEntry",
            main="false") {

...and the primary type would be declared:

  structure(Entry, desc="...", interface="AbstractCacheEntry") {
2015-07-20 09:15:18 -05:00
David Hashe
910638f338 slicc: Fix bug in enqueue and peek statements.
These were not generating the correct c names for types declared within a
machine scope.
2015-07-20 09:15:18 -05:00
David Hashe
3d8c8a85fa slicc: fix missing inline function in LocalVariableAST 2015-07-20 09:15:18 -05:00
David Hashe
93fff6f636 slicc: improve support for prefix operations
This patch fixes the type handling when prefix operations are used.  Previously
prefix operators would assume a void return type, which made it impossible to
combine prefix operations with other expressions.  This patch allows SLICC
programmers to use prefix operations more naturally.
2015-07-20 09:15:18 -05:00
David Hashe
ee0d414fa8 slicc: support for transitions with a wildcard next state
This patches adds support for transitions of the form:

transition(START, EVENTS, *) { ACTIONS }

This allows a machine to collapse states that differ only in the next state
transition to collapse into one, and can help shorten/simplfy some protocols
significantly.

When * is encountered as an end state of a transition, the next state is
determined by calling the machine-specific getNextState function. The next
state is determined before any actions of the transition execute, and
therefore the next state calculation cannot depend on any of the transition
actions.
2015-07-20 09:15:18 -05:00
David Hashe
6a288d9de3 slicc: support for multiple message types on the same buffer
This patch allows SLICC protocols to use more than one message type with a
message buffer. For example, you can declare two in ports as such:

  in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... }
  in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }
2015-07-20 09:15:18 -05:00
Brad Beckmann
b609b032aa slicc: fatal->panic on invalid transitions 2015-08-01 12:37:52 -04:00
David Hashe
3444d5f359 mem: Hit callback delay fix
This patch was created by Bihn Pham during his internship at AMD.

There is no need to delay hit callback response messages by a cycle because
the response latency is already incurred in the Ruby protocol. This ensures
correct timing of memory instructions.
2015-07-20 09:15:18 -05:00