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slicc: support for multiple cache entry types in the same state machine

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To have multiple Entry types (e.g., a cache Entry type and
a directory Entry type), just declare one of them as a secondary
type by using the pair 'main="false"', e.g.:

  structure(DirEntry, desc="...", interface="AbstractCacheEntry",
            main="false") {

...and the primary type would be declared:

  structure(Entry, desc="...", interface="AbstractCacheEntry") {
This commit is contained in:
David Hashe 2015-07-20 09:15:18 -05:00
parent 910638f338
commit 536e3664e4
1 changed files with 7 additions and 4 deletions
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11
src/mem/slicc/symbols/StateMachine.py
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@ -144,10 +144,13 @@ class StateMachine(Symbol):
self.TBEType = type
elif "interface" in type and "AbstractCacheEntry" == type["interface"]:
if self.EntryType != None:
self.error("Multiple AbstractCacheEntry types in a " \
"single machine.");
self.EntryType = type
if "main" in type and "false" == type["main"].lower():
pass # this isn't the EntryType
else:
if self.EntryType != None:
self.error("Multiple AbstractCacheEntry types in a " \
"single machine.");
self.EntryType = type
# Needs to be called before accessing the table
def buildTable(self):