Commit graph

9885 commits

Author SHA1 Message Date
Joel Hestness
82c6734f6b Configs: Fix handling of maxtick and take_checkpoints
In Simulation.py, calls to m5.simulate(num_ticks) will run the simulated system
for num_ticks after the current tick. Fix calls to m5.simulate in
scriptCheckpoints() and benchCheckpoints() to appropriately handle the maxticks
variable.
2013-04-09 16:25:30 -05:00
Joel Hestness
1583056de8 Ruby: Fix RubyPort evict packet memory leak
When using the o3 or inorder CPUs with many Ruby protocols, the caches may
need to forward invalidations to the CPUs. The RubyPort was instantiating a
packet to be sent to the CPUs to signal the eviction, but the packets were
not being freed by the CPUs. Consistent with the classic memory model, stack
allocate the packet and heap allocate the request so on
ruby_eviction_callback() completion, the packet deconstructor is called, and
deletes the request (*Note: stack allocating the request causes double
deletion, since it will be deleted in the packet destructor). This results in
the least memory allocations without memory errors.
2013-04-09 16:25:30 -05:00
Joel Hestness
46d4b71aa2 Ruby: Delete packet requests during warmup
When warming up caches in Ruby, the CacheRecorder sends fetch requests into
Ruby Sequencers with packet types that require responses. Since responses are
never generated for these CacheRecorder requests, the requests are not deleted
in the packet destructor called from the Ruby hit callback. Free the request.
2013-04-09 16:25:29 -05:00
Joel Hestness
e98c3c227d Ruby: Add field to slicc machine for generic type
This allows you to have (i.e.) an L2 cache that is not named "L2Cache"
but is still a GenericMachineType_L2Cache. This is particularly
helpful if the protocol has multiple L2 controllers.
2013-04-09 16:25:29 -05:00
Joel Hestness
b936619ab4 Ruby: Order profilers based on version
When Ruby stats are printed for events and transitions, they include stats
for all of the controllers of the same type, but they are not necessarily
printed in order of the controller ID "version", because of the way the
profilers were added to the profiler vector. This patch fixes the push order
problem so that the stats are printed in ascending order 0->(# controllers),
so statistics parsers may correctly assume the controller to which the stats
belong.
2013-04-09 16:25:29 -05:00
Jason Power
88d34665d0 Ruby: More descriptive message buffer connection fatal
When connecting message buffers between Ruby controllers, it is
easy to mistakenly connect multiple controllers to the same message
buffer. This patch prints a more descriptive fatal message than the
previous assert statement in order to facilitate easier debugging.
2013-04-09 16:15:06 -05:00
Jason Power
19cc9fc6bd Ruby: Fix typo in Slicc if-statement AST error
The error in the SLICC code was hidden by the python error in SLICC parser
before this patch
2013-04-09 16:12:42 -05:00
Joel Hestness
3b02210713 Ruby System, Cache Recorder: Use delete [] for trace vars
The cache trace variables are array allocated uint8_t* in the RubySystem and
the Ruby CacheRecorder, but the code used delete to free the memory, resulting
in Valgrind memory errors. Change these deletes to delete [] to get rid of the
errors.
2013-04-07 20:31:15 -05:00
Anthony Gutierrez
7fb55b98cc rcs scripts: remove bbench.rcS
this run script shouldn't be used; bbench-ics.rcS or bbench-gb.rcS
should be used instead.
2013-04-02 12:46:49 -04:00
Nilay Vaish
26e96b90e1 regressions: updates due to changes to o3 cpu, x86 memory map 2013-03-29 14:05:36 -05:00
Nilay Vaish
ac778b1d02 o3cpu: commit: changes interrupt handling
Currently the commit stage keeps a local copy of the interrupt object.
Since the interrupt is usually handled several cycles after the commit
stage becomes aware of it, it is possible that the local copy of the
interrupt object may not be the interrupt that is actually handled.
It is possible that another interrupt occurred in the
interval between interrupt detection and interrupt handling.

This patch creates a copy of the interrupt just before the interrupt
is handled. The local copy is ignored.
2013-03-29 14:05:26 -05:00
Nilay Vaish
d2fd3b2ec2 x86: changes to apic, keyboard
It is possible that operating system wants to shutdown the
lapic timer by writing timer's initial count to 0. This patch
adds a check that the timer event is only scheduled if the
count is 0.

The patch also converts few of the panics related to the keyboard
to warnings since we are any way not interested in simulating the
keyboard.
2013-03-28 09:34:23 -05:00
Nilay Vaish
433cab9d95 x86: create space in bios memory map
As of now, we mark the top 1MB of memory space as unusable. Part of
it is actually usable and is required to be marked so by some of the
newer versions of linux kernel. This patch marks the top 639KB as usable.
This value was chosen by looking at QEMU's output for bios memory map.
2013-03-28 09:34:15 -05:00
Nilay Vaish
1af9369779 regressions: update eio stats due to cache latency fix 2013-03-28 09:32:01 -05:00
Nilay Vaish
4646369afd regressions: update due to cache latency fix 2013-03-27 18:36:21 -05:00
Mitch Hayenga
4920f0d7e5 mem: Fix cache latency bug
Fixes a latency calculation bug for accesses during a cache line fill.

Under a cache miss, before the line is filled, accesses to the cache are
associated with a MSHR and marked as targets.  Once the line fill completes,
MSHR target packets pay an additional latency of
"responseLatency + busSerializationLatency".  However, the "whenReady"
field of the cache line is only set to an additional delay of
"busSerializationLatency".  This lacks the responseLatency component of
the fill.  It is possible for accesses that occur on the cycle of
(or briefly after) the line fill to respond without properly paying the
responseLatency.  This also creates the situation where two accesses to the
same address may be serviced in an order opposite of how they were received
by the cache.  For stores to the same address, this means that although the
cache performs the stores in the order they were received, acknowledgements
may be sent in a different order.

Adding the responseLatency component to the whenReady field preserves the
penalty that should be paid and prevents these ordering issues.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-03-27 18:36:09 -05:00
Steve Reinhardt
f0b745d556 scons: don't die on warnings in swig-generated code
There's not much to do about it other than disable the offending
warning anyway, so it's not worth terminating the build over.

Also suppress uninitialized variable warnings on gcc (happens
at least with gcc 4.4 and swig 1.3.40).
2013-03-27 10:03:02 -07:00
Andreas Hansson
2018f61c26 util: Add a utility script for decoding packet traces
This patch adds a simple Python script that reads the protobuf-encoded
packet traces (not gzipped), and prints them to an ASCII trace file.

The script can also be used as a template for other packet output
formats.
2013-03-26 14:49:58 -04:00
Andreas Hansson
7885a1646d util: Add a utility script for encoding packet traces
This patch adds a simple Python script that reads a simple ASCII trace
format and encodes it as protobuf output compatible with the traffic
generator.

The script can also be used as a template for other packet input
formats that should be converted to the gem5 packet protobuf format.
2013-03-26 14:49:55 -04:00
Andreas Hansson
a84d026538 stats: Update stats for cache retry event check
This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
2013-03-26 14:47:03 -04:00
Rene de Jong
87089175cc mem: Cancel cache retry event when blocking port
This patch solves the corner case scenario where the sendRetryEvent could be
scheduled twice, when an io device stresses the IOcache in the system. This
should not be possible in the cache system.
2013-03-26 14:46:51 -04:00
Andreas Hansson
08f7a8bc00 stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
2013-03-26 14:46:49 -04:00
Andreas Hansson
93a8423dea mem: Separate waiting for the bus and waiting for a peer
This patch splits the retryList into a list of ports that are waiting
for the bus itself to become available, and a map that tracks the
ports where forwarding failed due to a peer not accepting the
packet. Thus, when a retry reaches the bus, it can be sent to the
appropriate port that initiated that transaction.

As a consequence of this patch, only ports that are really ready to go
will get a retry, thus reducing the amount of redundant failed
attempts. This patch also makes it easier to reason about the order of
servicing requests as the ports waiting for the bus are now clearly
FIFO and much easier to change if desired.
2013-03-26 14:46:47 -04:00
Andreas Hansson
362f6f1a16 mem: Introduce a variable for the retrying port
This patch introduces a variable to keep track of the retrying port
instead of relying on it being the front of the retryList.

Besides the improvement in readability, this patch is a step towards
separating out the two cases where a port is waiting for the bus to be
free, and where the forwarding did not succeed and the bus is waiting
for a retry to pass on to the original initiator of the transaction.

The changes made are currently such that the regressions are not
affected. This is ensured by always prioritizing the currently
retrying port and putting it back at the front of the retry list.
2013-03-26 14:46:46 -04:00
Andreas Hansson
2123176684 mem: Add a generic id field to the packet trace
This patch adds an optional generic 64-bit identifier field to the
packet trace. This can be used to store the sequential number of the
instruction that gave rise to the packet, thread id, master id,
"sub"-master within a larger module etc. As the field is optional it
has a marginal cost if not used.
2013-03-26 14:46:45 -04:00
Andreas Hansson
7a57b1bce0 mem: Add optional request flags to the packet trace
This patch adds an optional flags field to the packet trace to encode
the request flags that contain information about whether the request
is (un)cacheable, instruction fetch, preftech etc.
2013-03-26 14:46:44 -04:00
Andreas Hansson
08c1835bef cpu: Remove CpuPort and use MasterPort in the CPU classes
This patch changes the port in the CPU classes to use MasterPort
instead of the derived CpuPort. The functions of the CpuPort are now
distributed across the relevant subclasses. The port accessor
functions (getInstPort and getDataPort) now return a MasterPort
instead of a CpuPort. This simplifies creating derivative CPUs that do
not use the CpuPort.
2013-03-26 14:46:42 -04:00
Andreas Sandberg
670fc52f18 x86: Revert [02321b16685f] which breaks m5ops on x86
Changeset 02321b16685f added m5_writefile to m5op_x86.S a second time,
which causes a compilation error on when compiling for x86. This
changeset reverts that changeset and fixes the error.
2013-03-25 13:20:15 +01:00
Nilay Vaish
546ffb2d6d config: return exit event instead of cause
changeset: a4739b6f799d made some changes that where an exit event
should have been returned in place of exit cause. This patch corrects
the error.
2013-03-22 17:31:24 -05:00
Nilay Vaish
04fe6b486a regressions: updates to config.ini for ruby tests 2013-03-22 17:21:25 -05:00
Nilay Vaish
b2c8c50f17 ruby: slicc: set sender, receiver clock objs for optional queue 2013-03-22 17:21:23 -05:00
Nilay Vaish
e85b556d70 ruby: message buffer: correct previous errors
A recent set of patches added support for multiple clock domains to ruby.
I had made some errors while writing those patches. The sender was using
the receiver side clock while enqueuing a message in the buffer. Those
errors became visible while creating (or restoring from) checkpoints. The
errors also become visible when a multi eventq scenario occurs.
2013-03-22 17:21:22 -05:00
Nilay Vaish
47c8cb72fc ruby: message buffer: remove _ptr from some variables
The names were getting too long.
2013-03-22 15:53:27 -05:00
Nilay Vaish
6465cf5824 ruby: message buffer node: used Tick in place of Cycles
The message buffer node used to keep time in terms of Cycles. Since the
sender and the receiver can have different clock periods, storing node
time in cycles requires some conversion. Instead store the time directly
in Ticks.
2013-03-22 15:53:26 -05:00
Nilay Vaish
39e9445468 ruby: consumer: avoid using receiver side clock
A set of patches was recently committed to allow multiple clock domains
in ruby. In those patches, I had inadvertently made an incorrect use of
the clocks. Suppose object A needs to schedule an event on object B. It
was possible that A accesses B's clock to schedule the event. This is not
possible in actual system. Hence, changes are being to the Consumer class
so as to avoid such happenings. Note that in a multi eventq simulation,
this can possibly lead to an incorrect simulation.

There are two functions in the Consumer class that are used for scheduling
events. The first function takes in the relative delay over the current time
as the argument and adds the current time to it for scheduling the event.
The second function takes in the absolute time (in ticks) for scheduling the
event. The first function is now being moved to protected section of the
class so that only objects of the derived classes can use it. All other
objects will have to specify absolute time while scheduling an event
for some consumer.
2013-03-22 15:53:26 -05:00
Nilay Vaish
28005a7626 ruby: remove unsued profile functions 2013-03-22 15:53:25 -05:00
Nilay Vaish
89bb826079 ruby: keep histogram of outstanding requests in seq
The histogram for tracking outstanding counts per cycle is maintained
in the profiler. For a parallel implementation of the memory system, we
need that this histogram is maintained locally. Hence it will now be
kept in the sequencer itself. The resulting histograms will be merged
when the stats are printed.
2013-03-22 15:53:25 -05:00
Nilay Vaish
870d545788 slicc: remove check if the L1Cache has a sequencer 2013-03-22 15:53:24 -05:00
Nilay Vaish
8573a69d8f ruby: move stall and wakeup functions to AbstractController
These functions are currently implemented in one of the files related to Slicc.
Since these are purely C++ functions, they are better suited to be in the base
class.
2013-03-22 15:53:24 -05:00
Nilay Vaish
eccc86e809 ruby: connect two controllers using only message buffers
This patch modifies ruby so that two controllers can be connected to each
other with only message buffers in between. Before this patch, all the
controllers had to be connected to the network  for them to communicate
with each other. With this patch, one can have protocols where a controller
is not connected to the network, but communicates with another controller
through a message buffer.
2013-03-22 15:53:23 -05:00
Nilay Vaish
5aa43e130a ruby: convert Topology to regular class
The Topology class in Ruby does not need to inherit from SimObject class.
This patch turns it into a regular class. The topology object is now created
in the constructor of the Network class. All the parameters for the topology
class have been moved to the network class.
2013-03-22 15:53:23 -05:00
Nilay Vaish
2d50127642 ruby: network: move routers from topology to network 2013-03-22 15:53:22 -05:00
Andreas Hansson
2ca42cd626 cpu: Avoid including inorder TLBUnit to avoid gcc LTO bug
This patch comments out the inclusion of the inorder TLBUnit which is
only used in the 9-stage pipeline. With the TLBUnit present, gcc >=
4.6 in combination with LTO ends up throwing away the definition of
the TLBUnit destructor, and consequently fail to link. See
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53808 for more details
about the bug, and http://gcc.gnu.org/ml/gcc/2012-06/msg00397.html for
the discussion thread that also touches on similar issues seen with
clang.
2013-03-20 06:41:23 -04:00
Andreas Sandberg
e28e6246fc scons: Try to use 'tcmalloc' before 'tcmalloc_minimal'
tcmalloc_minimal doesn't support the heap checker on Debian, while
tcmalloc does. Instead of always linking with tcmalloc_minimal, if it
exists, we first check for tcmalloc and then use tcmalloc_minimal as a
fallback.
2013-03-18 11:24:56 +01:00
Andreas Sandberg
468ad10f50 scons: Avoid malloc/free compiler optimization when using tcmalloc
According to the tcmalloc readme, the recommended way of compiling
applications that make use of tcmalloc is to disable compiler
optimizations that make assumptions about malloc and friends. This
changeset adds the necessary compiler flags for both gcc and clang.

From the tcmalloc readme:
"NOTE: When compiling with programs with gcc, that you plan to link
with libtcmalloc, it's safest to pass in the flags

 -fno-builtin-malloc -fno-builtin-calloc
 -fno-builtin-realloc -fno-builtin-free

when compiling."
2013-03-18 10:57:26 +01:00
Andreas Sandberg
9e9a47cb9a scons: Don't explicitly add tcmalloc_minimal to LIBS
SCons automatically adds a library to LIBS if conf.CheckLib succeeds,
so there is no need to explicitly add the library.
2013-03-18 10:44:34 +01:00
Andreas Sandberg
3e3475138b scons: Include flags required to link statically with Python
Python requires the flags in LINKFORSHARED to be added the linker
flags when linking with a statically with Python. Failing to do so can
lead to errors from the Python's dynamic module loader at start up.

--HG--
extra : rebase_source : e7a8daf72f4ede7ee5a4a5398a0b12e978a919b9
2013-03-18 10:22:21 +01:00
Andreas Hansson
c01c5e971b mem: Fix missing delete of packet in DRAM access
This patch fixes a memory leak caused by not deleting packets that
require no response.
2013-03-18 05:22:45 -04:00
Nilay Vaish
dc37b03439 ruby: set: corrects csprintf() call introduced by 7d95b650c9b6 2013-03-15 16:28:08 -05:00
Andreas Sandberg
9544e8fbe0 scons: Check for known buggy version of SWIG (2.0.9)
SWIG version 2.0.9 uses fully qualified module names despite of the
importing module being in the same package as the imported
module. This has the unfortunate consequence of causing the following
error when importing m5.internal.event:

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "src/python/m5/__init__.py", line 35, in <module>
    import internal
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "src/python/m5/internal/__init__.py", line 32, in <module>
    import event
  File "src/python/importer.py", line 75, in load_module
    exec code in mod.__dict__
  File "build/X86/python/swig/event.py", line 107, in <module>
    class Event(m5.internal.serialize.Serializable):
AttributeError: 'module' object has no attribute 'internal'

When 'event' is loaded, it triggers 'serialize' to be loaded. However,
it seems like the dictionary of 'm5' isn't updated until after
__init__.py terminates, which means that 'event' never sees the
'internal' attribute on 'm5'. Older versions of SWIG didn't include
the fully qualified module name if the modules were in the same
package.
2013-03-14 16:08:55 +01:00