Commit graph

12 commits

Author SHA1 Message Date
Kevin Lim
e3fb9afa79 Update to make multiple instruction issue and different latencies work.
Also change to ref counted DynInst.

SConscript:
    Add branch predictor, BTB, load store queue, and storesets.
arch/isa_parser.py:
    Specify the template parameter for AlphaDynInst
base/traceflags.py:
    Add load store queue, store set, and mem dependence unit to the
    list of trace flags.
cpu/base_dyn_inst.cc:
    Change formating, add in debug statement.
cpu/base_dyn_inst.hh:
    Change DynInst to be RefCounted, add flag to clear whether or not this
    instruction can commit.  This is likely to be removed in the future.
cpu/beta_cpu/alpha_dyn_inst.cc:
    AlphaDynInst has been changed to be templated, so now this CC file
    is just used to force instantiations of AlphaDynInst.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Changed AlphaDynInst to be templated on Impl.  Removed some unnecessary
    functions.
cpu/beta_cpu/alpha_full_cpu.cc:
    AlphaFullCPU has been changed to be templated, so this CC file is now
    just used to force instantation of AlphaFullCPU.
cpu/beta_cpu/alpha_full_cpu.hh:
    Change AlphaFullCPU to be templated on Impl.
cpu/beta_cpu/alpha_impl.hh:
    Update it to reflect AlphaDynInst and AlphaFullCPU being templated
    on Impl.  Also removed time buffers from here, as they are really
    a part of the CPU and are thus in the CPU policy now.
cpu/beta_cpu/alpha_params.hh:
    Make AlphaSimpleParams inherit from the BaseFullCPU so that it doesn't
    need to specifically declare any parameters that are already in the
    BaseFullCPU.
cpu/beta_cpu/comm.hh:
    Changed the structure of the time buffer communication structs.  Now
    they include the size of the packet of instructions it is sending.
    Added some parameters to the backwards communication struct, mainly
    for squashing.
cpu/beta_cpu/commit.hh:
    Update typenames to reflect change in location of time buffer structs.
    Update DynInst to DynInstPtr (it is refcounted now).
cpu/beta_cpu/commit_impl.hh:
    Formatting changes mainly.  Also sends back proper information
    on branch mispredicts so that the bpred unit can update itself.
    Updated behavior for non-speculative instructions (stores, any
    other non-spec instructions): once they reach the head of the ROB,
    the ROB signals back to the IQ that it can go ahead and issue the
    non-speculative instruction.  The instruction itself is updated so that
    commit won't try to commit it again until it is done executing.
cpu/beta_cpu/cpu_policy.hh:
    Added branch prediction unit, mem dependence prediction unit, load
    store queue.  Moved time buffer structs from AlphaSimpleImpl to here.
cpu/beta_cpu/decode.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and also the change from DynInst to ref counted DynInstPtr.
cpu/beta_cpu/decode_impl.hh:
    Continues to buffer instructions even while unblocking now.  Changed
    how it loops through groups of instructions so it can properly block
    during the middle of a group of instructions.
cpu/beta_cpu/fetch.hh:
    Changed typedefs to reflect change in location of time buffer structs
    and the change to ref counted DynInsts.  Also added in branch
    brediction unit.
cpu/beta_cpu/fetch_impl.hh:
    Add in branch prediction.  Changed how fetch checks inputs and its
    current state to make for easier logic.
cpu/beta_cpu/free_list.cc:
    Changed int regs and float regs to logically use one flat namespace.
    Future change will be moving them to a single scoreboard to conserve
    space.
cpu/beta_cpu/free_list.hh:
    Mostly debugging statements.  Might be removed for performance in future.
cpu/beta_cpu/full_cpu.cc:
    Added in some debugging statements.  Updated BaseFullCPU to take
    a params object.
cpu/beta_cpu/full_cpu.hh:
    Added params class within BaseCPU that other param classes will be
    able to inherit from.  Updated typedefs to reflect change in location
    of time buffer structs and ref counted DynInst.
cpu/beta_cpu/iew.hh:
    Updated typedefs to reflect change in location of time buffer structs
    and use of ref counted DynInsts.
cpu/beta_cpu/iew_impl.hh:
    Added in load store queue, updated iew to be able to execute non-
    speculative instructions, instead of having them execute in commit.
cpu/beta_cpu/inst_queue.hh:
    Updated change to ref counted DynInsts.  Changed inst queue to hold
    non-speculative instructions as well, which are issued only when
    commit signals backwards that a nonspeculative instruction is at
    the head of the ROB.
cpu/beta_cpu/inst_queue_impl.hh:
    Updated to allow for non-speculative instructions to be in the inst
    queue.  Also added some debug functions.
cpu/beta_cpu/regfile.hh:
    Added debugging statements, changed formatting.
cpu/beta_cpu/rename.hh:
    Updated typedefs, added some functions to clean up code.
cpu/beta_cpu/rename_impl.hh:
    Moved some code into functions to make it easier to read.
cpu/beta_cpu/rename_map.cc:
    Changed int and float reg behavior to use a single flat namespace.  In
    the future, the rename maps can be combined to a single rename map to
    save space.
cpu/beta_cpu/rename_map.hh:
    Added destructor.
cpu/beta_cpu/rob.hh:
    Updated it with change from DynInst to ref counted DynInst.
cpu/beta_cpu/rob_impl.hh:
    Formatting, updated to use ref counted DynInst.
cpu/static_inst.hh:
    Updated forward declaration for AlphaDynInst now that it is templated.

--HG--
extra : convert_revision : 1045f240ee9b6a4bd368e1806aca029ebbdc6dd3
2004-09-23 14:06:03 -04:00
Kevin Lim
04745696b6 Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches.
SConscript:
    Added new CPU files to build.
arch/alpha/isa_desc:
    Changed rduniq and wruniq to be nonspeculative because the uniq register is not renamed.
arch/isa_parser.py:
    Added new CPU exec method.
base/statistics.hh:
    Minor change for namespace conflict.  Probably can change back one the new CPU files are cleaned up.
base/traceflags.py:
    Added new CPU trace flags.
cpu/static_inst.hh:
    Changed static inst to use a file that defines the execute functions.

--HG--
extra : convert_revision : bd4ce34361308280168324817fc1258dd253e519
2004-08-20 14:54:07 -04:00
Steve Reinhardt
2c5356835d Split libelf/SConscript into two parts, one for the
shared build and one for the per-config header file
copying.

SConscript:
    Just include libelf/SConscript-local.
build/SConstruct:
    Include libelf/SConscript-global.

--HG--
extra : convert_revision : 0a4ae8f1514819f99fec101b898c19dabd4d59bd
2004-08-07 14:23:01 -07:00
Steve Reinhardt
d7dfe51fae Integrate Python configuration script parsing into m5 itself.
SConscript:
    Add pyconfig/{pyconfig,code}.cc
    Add list of object description (.od) files.
    Include pyconfig/SConscript.
base/inifile.cc:
    Get rid of CPP_PIPE... it never really worked anyway.
base/inifile.hh:
    Make load(ifstream&) method public so pyconfig
    code can call it.
sim/main.cc:
    Handle Python config scripts (end in '.py' instead of '.ini').
sim/pyconfig/m5configbase.py:
    Add license.
    Fix minor __setattr__ problem (2.3 related?)

--HG--
rename : util/config/m5configbase.py => sim/pyconfig/m5configbase.py
extra : convert_revision : 5e004922f950bfdefced333285584b80ad7ffb83
2004-08-05 02:03:47 -07:00
Steve Reinhardt
1939370c96 Move libelf/SConscript include to m5/SConscript, so elf
headers get created in build tree (under build/FOO/libelf)
instead of source tree (m5/libelf).

SConscript:
    Move libelf/SConscript include here.
build/SConstruct:
    Get rid of libelf/SConscript include (moved to
    m5/SConscript).

--HG--
extra : convert_revision : c0acb3bab2afa5079748b907c5917f548582099e
2004-08-03 22:46:03 -07:00
Lisa Hsu
ec3a9e3cfc added printk.cc to the sconsscript so it will actually build.
SConscript:
    grrr, spent half an hour looking for why the linker was dying.  needed to include the new file printk.cc

--HG--
extra : convert_revision : 4c461d9dbe96e94d7c312bf71ee8ad4c87a3b1a1
2004-07-30 21:14:05 -04:00
Nathan Binkert
3711ea7347 Move all of the object matching code to a shared file so it can
be more easily re-used.  This currently uses some cooked up matching
function that I wrote a while ago, but should probably be changed
to use regular expressions in the future.
add doDebugBreak to control breakpoints on a per SimObject basis

SConscript:
    add match
base/stats/events.cc:
base/trace.cc:
    Move the object matching code into a separate file so it can be
    more easily shared
base/trace.hh:
    the object matching code was wrapped up and moved.  adapt.
sim/sim_object.cc:
    add the doDebugBreak flag that can be set on a per-SimObject
    basis.  This will be used in the future to control whether or
    not debug_break() will actually break for a given object.

    provide a function interface that can be called from the debugger.
sim/sim_object.hh:
    add the doDebugBreak flag that can be set on a per-SimObject
    basis.  This will be used in the future to control whether or
    not debug_break() will actually break for a given object.

--HG--
extra : convert_revision : 6bf7924de63d41f5ba6b80d579efdf26ba265a8f
2004-07-30 10:47:53 -04:00
Steve Reinhardt
374e12c2de Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5

--HG--
extra : convert_revision : c79927401293a4496223cf190b9fc6cab6ea12de
2004-07-14 15:48:19 -04:00
Steve Reinhardt
842da6a9bb SConscript:
Make decoder.cc/hh depend on isa_parser.py.

SConscript:
    Make decoder.cc/hh depend on isa_parser.py.

--HG--
extra : convert_revision : ff575d7f819da951423b36275e960fed652f9b2b
2004-07-14 15:48:11 -04:00
Lisa Hsu
9dc9523a1c the changeset of partitioned caches. this changeset creates Split tagstore class that makes either an LRU/LRU cache or a LRU/LIFO cache, it is also able to make just a LIFO cache.
SConscript:
    add these files for partitioned caches
base/traceflags.py:
    add Split as a traceflag

--HG--
extra : convert_revision : 6aa8f7c389ee1145b33be006c820236f11f5397c
2004-07-10 21:57:59 -04:00
Lisa Hsu
9dba9e462f fix the failing regression. the sconscript ("makefile") was missing the etherbus.cc src file.
SConscript:
    THIS is why the regression keeps failing.  it's missing the the etherbus file in the sconscript.

--HG--
extra : convert_revision : adbcfb6036d8e8ecb51c4f484d0030059542684b
2004-07-08 09:05:26 -04:00
Steve Reinhardt
b13e28afbb Initial SCons-based build system. See www.scons.org.
'cd build; scons' will build ALPHA/m5.debug.
Use e.g. 'scons KERNEL/m5.opt' to build other binaries.
Read the comments in build/SConstruct for more details.

base/traceflags.py:
    Take basename of generated cc/hh files from command line instead
    of hardwiring them.  Lets us call the script from a different
    directory and still have the files end up in the right place
    (e.g. "base/traceflags.py base/traceflags").

--HG--
extra : convert_revision : ee4dbb59040cf07590929275f6c1c01e8d4e00b4
2004-07-02 21:16:38 -07:00