Commit graph

15 commits

Author SHA1 Message Date
Curtis Dunham
31825bd988 sim, arm: add checkpoint upgrader for d02b45a5
The insertion of CONTEXTIDR_EL2 in the ARM miscellaneous registers
obsoletes old checkpoints.
2015-06-01 18:05:11 -05:00
Curtis Dunham
4a3f11149d arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86).  Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
2014-04-29 16:05:02 -05:00
Curtis Dunham
04d1f61ae8 sim: bump checkpoint version for multiple event queues
This patch adds a fix for older checkpoints before support for
multiple event queues were added in changeset 2cce74fe359e. The change
in checkpoint version should really hav ebeen part of the
aforementioned changeset.
2014-02-05 16:17:41 -06:00
Radhika Jagtap
b998a0c6ac util: Add DVFS perfLevel to checkpoint upgrade script
This patch updates the checkpoint upgrader script. It adds the _perfLevel
variable in the clock domain and voltage domain simObjects used for DVFS.
2014-07-01 11:58:22 -04:00
Marco Elver
d9fa950396 ruby: recorder: Fix (de-)serializing with different cache block-sizes
Upon aggregating records, serialize system's cache-block size, as the
cache-block size can be different when restoring from a checkpoint. This way,
we can correctly read all records when restoring from a checkpoints, even if
the cache-block size is different.

Note, that it is only possible to restore from a checkpoint if the
desired cache-block size is smaller or equal to the cache-block size
when the checkpoint was taken; we can split one larger request into
multiple small ones, but it is not reliable to do the opposite.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-19 09:00:30 -05:00
ARM gem5 Developers
612f8f074f arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli    (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt       (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole           (AArch64 NEON, validation)
Ali Saidi            (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang         (AArch64 Linux support)
Rene De Jong         (AArch64 Linux support, performance opt.)
Matt Horsnell        (AArch64 MP, validation)
Matt Evans           (device models, code integration, validation)
Chris Adeniyi-Jones  (AArch64 syscall-emulation)
Prakash Ramrakhyani  (validation)
Dam Sunwoo           (validation)
Chander Sudanthi     (validation)
Stephan Diestelhorst (validation)
Andreas Hansson      (code integration, performance opt.)
Eric Van Hensbergen  (performance opt.)
Gabe Black
2014-01-24 15:29:34 -06:00
Chander Sudanthi
3e6da89419 ARM: add support for TEEHBR access
Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier
in arch/arm/kernel/thumbee.c.  The Linux kernel code just seems
to be saving and restoring the register.  This patch adds support
for the TEEHBR cp14 register.  Note, this may be a special case
when restoring from an image that was run on a system that
supports ThumbEE.
2013-10-31 13:41:13 -05:00
Geoffrey Blake
be4aa2b6ba dev: Fix race conditions in IDE device on newer kernels
Newer linux kernels and distros exercise more functionality in the IDE device
than previously, exposing 2 races. The first race is the handling of aborted
DMA commands would immediately report the device is ready back to the kernel
and cause already in flight commands to assert the simulator when they returned
and discovered an inconsitent device state.  The second race was due to the
Status register not being handled correctly, the interrupt status bit would get
stuck at 1 and the driver eventually views this as a bad state and logs the
condition to the terminal.  This patch fixes these two conditions by making the
device handle aborted commands gracefully and properly handles clearing the
interrupt status bit in the Status register.
2013-10-31 13:41:13 -05:00
Nilay Vaish
e038741598 x86: add tlb checkpointing
This patch adds checkpointing support to x86 tlb. It upgrades the
cpt_upgrader.py script so that previously created checkpoints can
be updated. It moves the checkpoint version to 6.
2013-08-07 14:51:17 -05:00
Andreas Sandberg
38925ff621 arm: Remove the register mapping hack used when copying TCs
In order to see all registers independent of the current CPU mode, the
ARM architecture model uses the magic MISCREG_CPSR_MODE register to
change the register mappings without actually updating the CPU
mode. This hack is no longer needed since the thread context now
provides a flat interface to the register file. This patch replaces
the CPSR_MODE hack with the flat register interface.
2013-01-07 13:05:44 -05:00
Andreas Sandberg
17b47d35e1 arch: Move the ISA object to a separate section
After making the ISA an independent SimObject, it is serialized
automatically by the Python world. Previously, this just resulted in
an empty ISA section. This patch moves the contents of the ISA to that
section and removes the explicit ISA serialization from the thread
contexts, which makes it behave like a normal SimObject during
serialization.

Note: This patch breaks checkpoint backwards compatibility! Use the
cpt_upgrader.py utility to upgrade old checkpoints to the new format.
2013-01-07 13:05:42 -05:00
Dam Sunwoo
81406018b0 ARM: dump stats and process info on context switches
This patch enables dumping statistics and Linux process information on
context switch boundaries (__switch_to() calls) that are used for
Streamline integration (a graphical statistics viewer from ARM).
2012-11-02 11:32:01 -05:00
Andreas Hansson
9baa35ba80 Mem: Separate the host and guest views of memory backing store
This patch moves all the memory backing store operations from the
independent memory controllers to the global physical memory. The main
reason for this patch is to allow address striping in a future set of
patches, but at this point it already provides some useful
functionality in that it is now possible to change the number of
memory controllers and their address mapping in combination with
checkpointing. Thus, the host and guest view of the memory backing
store are now completely separate.

With this patch, the individual memory controllers are far simpler as
all responsibility for serializing/unserializing is moved to the
physical memory. Currently, the functionality is more or less moved
from AbstractMemory to PhysicalMemory without any major
changes. However, in a future patch the physical memory will also
resolve any ranges that are interleaved and properly assign the
backing store to the memory controllers, and keep the host memory as a
single contigous chunk per address range.

Functionality for future extensions which involve CPU virtualization
also enable the host to get pointers to the backing store.
2012-10-15 08:12:32 -04:00
Ali Saidi
c06970b673 cpt: update some comments in the checkpoint migration script 2012-06-05 10:36:59 -04:00
Ali Saidi
70d7d6cc7f sim: Provide a framework for detecting out of data checkpoints and migrating them. 2012-06-05 01:23:10 -04:00