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arch: Move the ISA object to a separate section

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After making the ISA an independent SimObject, it is serialized
automatically by the Python world. Previously, this just resulted in
an empty ISA section. This patch moves the contents of the ISA to that
section and removes the explicit ISA serialization from the thread
contexts, which makes it behave like a normal SimObject during
serialization.

Note: This patch breaks checkpoint backwards compatibility! Use the
cpt_upgrader.py utility to upgrade old checkpoints to the new format.
This commit is contained in:
Andreas Sandberg 2013-01-07 13:05:42 -05:00
parent 7eb0fb8b6e
commit 17b47d35e1
12 changed files with 84 additions and 49 deletions
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4
src/arch/alpha/isa.cc
View file

@ -53,7 +53,7 @@ ISA::params() const
}
void
ISA::serialize(EventManager *em, std::ostream &os)
ISA::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(fpcr);
SERIALIZE_SCALAR(uniq);
@ -63,7 +63,7 @@ ISA::serialize(EventManager *em, std::ostream &os)
}
void
ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
ISA::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(fpcr);
UNSERIALIZE_SCALAR(uniq);

5
src/arch/alpha/isa.hh
View file

@ -88,9 +88,8 @@ namespace AlphaISA
memset(ipr, 0, sizeof(ipr));
}
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
int
flattenIntIndex(int reg)

5
src/arch/arm/isa.hh
View file

@ -180,13 +180,12 @@ namespace ArmISA
return reg;
}
void serialize(EventManager *em, std::ostream &os)
void serialize(std::ostream &os)
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
}
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section)
void unserialize(Checkpoint *cp, const std::string &section)
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);

6
src/arch/mips/isa.hh
View file

@ -172,12 +172,6 @@ namespace MipsISA
{
return reg;
}
void serialize(EventManager *em, std::ostream &os)
{}
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section)
{}
};
}

10
src/arch/power/isa.hh
View file

@ -98,16 +98,6 @@ class ISA : public SimObject
return reg;
}
void
serialize(EventManager *em, std::ostream &os)
{
}
void
unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
{
}
const Params *params() const;
ISA(Params *p);

10
src/arch/sparc/isa.cc
View file

@ -638,7 +638,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
}
void
ISA::serialize(EventManager *em, std::ostream &os)
ISA::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(asi);
SERIALIZE_SCALAR(tick);
@ -714,7 +714,7 @@ ISA::serialize(EventManager *em, std::ostream &os)
}
void
ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
ISA::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(asi);
UNSERIALIZE_SCALAR(tick);
@ -781,15 +781,15 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
if (tick_cmp) {
tickCompare = new TickCompareEvent(this, tc);
em->schedule(tickCompare, tick_cmp);
schedule(tickCompare, tick_cmp);
}
if (stick_cmp) {
sTickCompare = new STickCompareEvent(this, tc);
em->schedule(sTickCompare, stick_cmp);
schedule(sTickCompare, stick_cmp);
}
if (hstick_cmp) {
hSTickCompare = new HSTickCompareEvent(this, tc);
em->schedule(hSTickCompare, hstick_cmp);
schedule(hSTickCompare, hstick_cmp);
}
}
}

5
src/arch/sparc/isa.hh
View file

@ -167,10 +167,9 @@ class ISA : public SimObject
void clear();
void serialize(EventManager *em, std::ostream & os);
void serialize(std::ostream & os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string & section);
void unserialize(Checkpoint *cp, const std::string & section);
protected:

5
src/arch/x86/isa.cc
View file

@ -370,14 +370,13 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
}
void
ISA::serialize(EventManager *em, std::ostream & os)
ISA::serialize(std::ostream & os)
{
SERIALIZE_ARRAY(regVal, NumMiscRegs);
}
void
ISA::unserialize(EventManager *em, Checkpoint * cp,
const std::string & section)
ISA::unserialize(Checkpoint * cp, const std::string & section)
{
UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
updateHandyM5Reg(regVal[MISCREG_EFER],

5
src/arch/x86/isa.hh
View file

@ -85,9 +85,8 @@ namespace X86ISA
return reg;
}
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
}

10
src/cpu/simple_thread.cc
View file

@ -179,11 +179,6 @@ SimpleThread::serialize(ostream &os)
SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
_pcState.serialize(os);
// thread_num and cpu_id are deterministic from the config
//
// Now must serialize all the ISA dependent state
//
isa->serialize(baseCpu, os);
}
@ -195,11 +190,6 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
_pcState.unserialize(cp, section);
// thread_num and cpu_id are deterministic from the config
//
// Now must unserialize all the ISA dependent state
//
isa->unserialize(baseCpu, cp, section);
}
void

2
src/sim/serialize.hh
View file

@ -57,7 +57,7 @@ class SimObject;
* SimObject shouldn't cause the version number to increase, only changes to
* existing objects such as serializing/unserializing more state, changing sizes
* of serialized arrays, etc. */
static const uint64_t gem5CheckpointVersion = 0x0000000000000003;
static const uint64_t gem5CheckpointVersion = 0x0000000000000004;
template <class T>
void paramOut(std::ostream &os, const std::string &name, const T &param);

66
util/cpt_upgrader.py
View file

@ -116,11 +116,77 @@ def from_2(cpt):
except ConfigParser.NoOptionError:
pass
# The ISA is now a separate SimObject, which means that we serialize
# it in a separate section instead of as a part of the ThreadContext.
def from_3(cpt):
isa = cpt.get('root','isa')
isa_fields = {
"alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ),
"arm" : ( "miscRegs" ),
"sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",
"stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt",
"tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate",
"htstate", "hintp", "htba", "hstick_cmpr",
"strandStatusReg", "fsr", "priContext", "secContext",
"partId", "lsuCtrlReg", "scratchPad",
"cpu_mondo_head", "cpu_mondo_tail",
"dev_mondo_head", "dev_mondo_tail",
"res_error_head", "res_error_tail",
"nres_error_head", "nres_error_tail",
"tick_intr_sched",
"cpu", "tc_num", "tick_cmp", "stick_cmp", "hstick_cmp"),
"x86" : ( "regVal" ),
}
isa_fields = isa_fields.get(isa, [])
isa_sections = []
for sec in cpt.sections():
import re
re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec)
# Search for all the execution contexts
if not re_cpu_match:
continue
if re_cpu_match.group(2) != "0":
# This shouldn't happen as we didn't support checkpointing
# of in-order and O3 CPUs.
raise ValueError("Don't know how to migrate multi-threaded CPUs "
"from version 1")
isa_section = []
for fspec in isa_fields:
for (key, value) in cpt.items(sec, raw=True):
if key in isa_fields:
isa_section.append((key, value))
name = "%s.isa" % re_cpu_match.group(1)
isa_sections.append((name, isa_section))
for (key, value) in isa_section:
cpt.remove_option(sec, key)
for (sec, options) in isa_sections:
# Some intermediate versions of gem5 have empty ISA sections
# (after we made the ISA a SimObject, but before we started to
# serialize into a separate ISA section).
if not cpt.has_section(sec):
cpt.add_section(sec)
else:
if cpt.items(sec):
raise ValueError("Unexpected populated ISA section in old "
"checkpoint")
for (key, value) in options:
cpt.set(sec, key, value)
migrations = []
migrations.append(from_0)
migrations.append(from_1)
migrations.append(from_2)
migrations.append(from_3)
verbose_print = False