be4aa2b6ba
Newer linux kernels and distros exercise more functionality in the IDE device than previously, exposing 2 races. The first race is the handling of aborted DMA commands would immediately report the device is ready back to the kernel and cause already in flight commands to assert the simulator when they returned and discovered an inconsitent device state. The second race was due to the Status register not being handled correctly, the interrupt status bit would get stuck at 1 and the driver eventually views this as a bad state and logs the condition to the terminal. This patch fixes these two conditions by making the device handle aborted commands gracefully and properly handles clearing the interrupt status bit in the Status register.
332 lines
13 KiB
Python
Executable file
332 lines
13 KiB
Python
Executable file
#!/usr/bin/env python
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# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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#
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# This python code is used to migrate checkpoints that were created in one
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# version of the simulator to newer version. As features are added or bugs are
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# fixed some of the state that needs to be checkpointed can change. If you have
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# many historic checkpoints that you use, manually editing them to fix them is
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# both time consuming and error-prone.
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# This script provides a way to migrate checkpoints to the newer repository in
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# a programatic way. It can be imported into another script or used on the
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# command line. From the command line the script will either migrate every
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# checkpoint it finds recursively (-r option) or a single checkpoint. When a
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# change is made to the gem5 repository that breaks previous checkpoints a
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# from_N() method should be implemented here and the gem5CheckpointVersion
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# variable in src/sim/serialize.hh should be incremented. For each version
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# between the checkpoints current version and the new version the from_N()
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# method will be run, passing in a ConfigParser object which contains the open
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# file. As these operations can be isa specific the method can verify the isa
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# and use regexes to find the correct sections that need to be updated.
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import ConfigParser
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import sys, os
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import os.path as osp
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# An example of a translator
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def from_0(cpt):
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if cpt.get('root','isa') == 'arm':
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for sec in cpt.sections():
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import re
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# Search for all the execution contexts
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if re.search('.*sys.*\.cpu.*\.x.\..*', sec):
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# Update each one
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mr = cpt.get(sec, 'miscRegs').split()
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#mr.insert(21,0)
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#mr.insert(26,0)
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cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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# The backing store supporting the memories in the system has changed
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# in that it is now stored globally per address range. As a result the
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# actual storage is separate from the memory controllers themselves.
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def from_1(cpt):
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for sec in cpt.sections():
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import re
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# Search for a physical memory
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if re.search('.*sys.*\.physmem$', sec):
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# Add the number of stores attribute to the global physmem
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cpt.set(sec, 'nbr_of_stores', '1')
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# Get the filename and size as this is moving to the
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# specific backing store
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mem_filename = cpt.get(sec, 'filename')
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mem_size = cpt.get(sec, '_size')
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cpt.remove_option(sec, 'filename')
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cpt.remove_option(sec, '_size')
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# Get the name so that we can create the new section
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system_name = str(sec).split('.')[0]
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section_name = system_name + '.physmem.store0'
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cpt.add_section(section_name)
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cpt.set(section_name, 'store_id', '0')
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cpt.set(section_name, 'range_size', mem_size)
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cpt.set(section_name, 'filename', mem_filename)
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elif re.search('.*sys.*\.\w*mem$', sec):
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# Due to the lack of information about a start address,
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# this migration only works if there is a single memory in
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# the system, thus starting at 0
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raise ValueError("more than one memory detected (" + sec + ")")
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def from_2(cpt):
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for sec in cpt.sections():
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import re
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# Search for a CPUs
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if re.search('.*sys.*cpu', sec):
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try:
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junk = cpt.get(sec, 'instCnt')
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cpt.set(sec, '_pid', '0')
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except ConfigParser.NoOptionError:
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pass
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# The ISA is now a separate SimObject, which means that we serialize
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# it in a separate section instead of as a part of the ThreadContext.
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def from_3(cpt):
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isa = cpt.get('root','isa')
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isa_fields = {
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"alpha" : ( "fpcr", "uniq", "lock_flag", "lock_addr", "ipr" ),
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"arm" : ( "miscRegs" ),
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"sparc" : ( "asi", "tick", "fprs", "gsr", "softint", "tick_cmpr",
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"stick", "stick_cmpr", "tpc", "tnpc", "tstate", "tt",
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"tba", "pstate", "tl", "pil", "cwp", "gl", "hpstate",
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"htstate", "hintp", "htba", "hstick_cmpr",
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"strandStatusReg", "fsr", "priContext", "secContext",
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"partId", "lsuCtrlReg", "scratchPad",
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"cpu_mondo_head", "cpu_mondo_tail",
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"dev_mondo_head", "dev_mondo_tail",
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"res_error_head", "res_error_tail",
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"nres_error_head", "nres_error_tail",
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"tick_intr_sched",
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"cpu", "tc_num", "tick_cmp", "stick_cmp", "hstick_cmp"),
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"x86" : ( "regVal" ),
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}
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isa_fields = isa_fields.get(isa, [])
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isa_sections = []
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for sec in cpt.sections():
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import re
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re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec)
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# Search for all the execution contexts
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if not re_cpu_match:
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continue
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if re_cpu_match.group(2) != "0":
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# This shouldn't happen as we didn't support checkpointing
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# of in-order and O3 CPUs.
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raise ValueError("Don't know how to migrate multi-threaded CPUs "
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"from version 1")
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isa_section = []
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for fspec in isa_fields:
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for (key, value) in cpt.items(sec, raw=True):
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if key in isa_fields:
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isa_section.append((key, value))
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name = "%s.isa" % re_cpu_match.group(1)
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isa_sections.append((name, isa_section))
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for (key, value) in isa_section:
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cpt.remove_option(sec, key)
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for (sec, options) in isa_sections:
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# Some intermediate versions of gem5 have empty ISA sections
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# (after we made the ISA a SimObject, but before we started to
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# serialize into a separate ISA section).
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if not cpt.has_section(sec):
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cpt.add_section(sec)
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else:
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if cpt.items(sec):
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raise ValueError("Unexpected populated ISA section in old "
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"checkpoint")
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for (key, value) in options:
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cpt.set(sec, key, value)
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# Version 5 of the checkpoint format removes the MISCREG_CPSR_MODE
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# register from the ARM register file.
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def from_4(cpt):
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if cpt.get('root','isa') == 'arm':
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for sec in cpt.sections():
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import re
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# Search for all ISA sections
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if re.search('.*sys.*\.cpu.*\.isa', sec):
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mr = cpt.get(sec, 'miscRegs').split()
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# Remove MISCREG_CPSR_MODE
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del mr[137]
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cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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# Version 6 of the checkpoint format adds tlb to x86 checkpoints
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def from_5(cpt):
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if cpt.get('root','isa') == 'x86':
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for sec in cpt.sections():
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import re
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# Search for all ISA sections
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if re.search('.*sys.*\.cpu.*\.dtb$', sec):
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cpt.set(sec, '_size', '0')
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cpt.set(sec, 'lruSeq', '0')
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if re.search('.*sys.*\.cpu.*\.itb$', sec):
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cpt.set(sec, '_size', '0')
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cpt.set(sec, 'lruSeq', '0')
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else:
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print "ISA is not x86"
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# Version 7 of the checkpoint adds support for the IDE dmaAbort flag
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def from_6(cpt):
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# Update IDE disk devices with dmaAborted
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for sec in cpt.sections():
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# curSector only exists in IDE devices, so key on that attribute
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if cpt.has_option(sec, "curSector"):
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cpt.set(sec, "dmaAborted", "false")
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migrations = []
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migrations.append(from_0)
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migrations.append(from_1)
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migrations.append(from_2)
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migrations.append(from_3)
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migrations.append(from_4)
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migrations.append(from_5)
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migrations.append(from_6)
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verbose_print = False
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def verboseprint(*args):
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if not verbose_print:
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return
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for arg in args:
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print arg,
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print
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def process_file(path, **kwargs):
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if not osp.isfile(path):
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import errno
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raise IOError(ennro.ENOENT, "No such file", path)
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verboseprint("Processing file %s...." % path)
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if kwargs.get('backup', True):
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import shutil
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shutil.copyfile(path, path + '.bak')
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cpt = ConfigParser.SafeConfigParser()
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# gem5 is case sensitive with paramaters
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cpt.optionxform = str
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# Read the current data
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cpt_file = file(path, 'r')
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cpt.readfp(cpt_file)
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cpt_file.close()
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# Make sure we know what we're starting from
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if not cpt.has_option('root','cpt_ver'):
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raise LookupError("cannot determine version of checkpoint")
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cpt_ver = cpt.getint('root','cpt_ver')
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# If the current checkpoint is longer than the migrations list, we have a problem
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# and someone didn't update this file
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if cpt_ver > len(migrations):
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raise ValueError("upgrade script is too old and needs updating")
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verboseprint("\t...file is at version %#x" % cpt_ver)
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if cpt_ver == len(migrations):
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verboseprint("\t...nothing to do")
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return
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# Walk through every function from now until the end fixing the checkpoint
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for v in xrange(cpt_ver,len(migrations)):
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verboseprint("\t...migrating to version %#x" % (v + 1))
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migrations[v](cpt)
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cpt.set('root','cpt_ver', str(v + 1))
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# Write the old data back
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verboseprint("\t...completed")
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cpt.write(file(path, 'w'))
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if __name__ == '__main__':
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from optparse import OptionParser
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parser = OptionParser("usage: %prog [options] <filename or directory>")
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parser.add_option("-r", "--recurse", action="store_true",
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help="Recurse through all subdirectories modifying "\
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"each checkpoint that is found")
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parser.add_option("-N", "--no-backup", action="store_false",
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dest="backup", default=True,
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help="Do no backup each checkpoint before modifying it")
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parser.add_option("-v", "--verbose", action="store_true",
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help="Print out debugging information as")
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(options, args) = parser.parse_args()
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if len(args) != 1:
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parser.error("You must specify a checkpoint file to modify or a "\
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"directory of checkpoints to recursively update")
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verbose_print = options.verbose
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# Deal with shell variables and ~
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path = osp.expandvars(osp.expanduser(args[0]))
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# Process a single file if we have it
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if osp.isfile(path):
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process_file(path, **vars(options))
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# Process an entire directory
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elif osp.isdir(path):
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cpt_file = osp.join(path, 'm5.cpt')
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if options.recurse:
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# Visit very file and see if it matches
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for root,dirs,files in os.walk(path):
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for name in files:
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if name == 'm5.cpt':
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process_file(osp.join(root,name), **vars(options))
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for dir in dirs:
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pass
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# Maybe someone passed a cpt.XXXXXXX directory and not m5.cpt
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elif osp.isfile(cpt_file):
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process_file(cpt_file, **vars(options))
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else:
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print "Error: checkpoint file not found at in %s " % path,
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print "and recurse not specified"
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sys.exit(1)
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sys.exit(0)
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