Commit graph

7910 commits

Author SHA1 Message Date
Joel Hestness
dedb4fbf05 Ruby: Fix to return cache block size to CPU for split data transfers 2011-02-06 22:14:18 -08:00
Joel Hestness
82844618fd Ruby: Add support for locked memory accesses in X86_FS 2011-02-06 22:14:18 -08:00
Joel Hestness
16c1edebd0 Ruby: Update the Ruby request type names for LL/SC 2011-02-06 22:14:18 -08:00
Brad Beckmann
9782ca5def ruby: Assert for x86 misaligned access
This patch ensures only aligned access are passed to ruby and includes a fix
to the DPRINTF address print.
2011-02-06 22:14:18 -08:00
Brad Beckmann
17b4ef52bb ruby: x86 fs config support 2011-02-06 22:14:18 -08:00
Brad Beckmann
1b54344aeb MOESI_hammer: Added full-bit directory support 2011-02-06 22:14:18 -08:00
Joel Hestness
62e05ed78a x86: Add checkpointing capability to devices
Add checkpointing capability to the Intel 8254 timer, CMOS, I8042,
PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker
devices
2011-02-06 22:14:18 -08:00
Joel Hestness
911ccef6c0 x86: Add checkpointing capability to arch components
Add checkpointing capability to the x86 interrupt device and the TLBs
2011-02-06 22:14:17 -08:00
Joel Hestness
38140b5519 x86: implements vtophys
Calls walker to look up virt. to phys. page mapping
2011-02-06 22:14:17 -08:00
Joel Hestness
eea78f968b IntDev: packet latency fix
The x86 local apic now includes a separate latency parameter for interrupts.
2011-02-06 22:14:17 -08:00
Joel Hestness
d9f0a8288e MessagePort: implement the virtual recvTiming function to avoid double pkt delete
Double packet delete problem is due to an interrupt device deleting a packet that the SimpleTimingPort also deletes. Since MessagePort descends from SimpleTimingPort, simply reimplement the failing code from SimpleTimingPort: recvTiming.
2011-02-06 22:14:17 -08:00
Joel Hestness
02b05bf9be MOESI_hammer: trigge queue fix. 2011-02-06 22:14:17 -08:00
Joel Hestness
b4c10bd680 mcpat: Adds McPAT performance counters
Updated patches from Rick Strong's set that modify performance counters for
McPAT
2011-02-06 22:14:17 -08:00
Tushar Krishna
a679e732ce garnet: added orion2.0 for network power calculation 2011-02-06 22:14:17 -08:00
Tushar Krishna
59163f824c garnet: separate data and ctrl VCs
Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per VC,
while data VCs have > 1 buffers per VC. This is for correct power estimations.
2011-02-06 22:14:16 -08:00
Brad Beckmann
afd754dc0d x86: set IsCondControl flag for the appropriate microops 2011-02-06 22:14:16 -08:00
Gabe Black
55df9e348c X86: Add o3 regressions in SE mode.
Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 00:16:09 -08:00
Gabe Black
0aafbe4098 X86: Update ruby stats for stupd change. 2011-02-04 03:47:23 -08:00
Gabe Black
aa62c217c5 Fault: Forgot to refresh to grab these header guard updates. 2011-02-03 22:07:34 -08:00
Korey Sewell
a48fe2729a imported patch regression_updates 2011-02-04 00:09:22 -05:00
Korey Sewell
e396a34b01 inorder: fault handling
Maintain all information about an instruction's fault in the DynInst object rather
than any cpu-request object. Also, if there is a fault during the execution stage
then just save the fault inside the instruction and trap once the instruction
tries to graduate
2011-02-04 00:09:20 -05:00
Korey Sewell
e57613588b inorder: pcstate and delay slots bug
not taken delay slots were not being advanced correctly to pc+8, so for those ISAs
we 'advance()' the pcstate one more time for the desired effect
2011-02-04 00:09:19 -05:00
Korey Sewell
68d962f8af inorder: add a fetch buffer to fetch unit
Give fetch unit it's own parameterizable fetch buffer to read from. Very inefficient
(architecturally and in simulation) to continually fetch at the granularity of the
wordsize. As expected, the number of fetch memory requests drops dramatically
2011-02-04 00:08:22 -05:00
Korey Sewell
56ce8acd41 inorder: overload find-req fn
no need to have separate function name findSplitRequest, just overload the function
2011-02-04 00:08:21 -05:00
Korey Sewell
ab3d37d398 inorder: implement separate fetch unit
instead of having one cache-unit class be responsible for both data and code
accesses, separate code that is just for fetch in it's own derived class off the
original base class. This makes the code easier to manage as well as handle
future cases of special fetch handling
2011-02-04 00:08:20 -05:00
Korey Sewell
f80508de65 inorder: cache port blocking
set the request to false when the cache port blocks so we dont deadlock.
also, comment out the outstanding address list sanity check for now.
2011-02-04 00:08:19 -05:00
Korey Sewell
0c6a679359 inorder: stage width as a python parameter
allow the user to specify how many instructions a pipeline stage can process
on any given cycle (stageWidth...i.e.bandwidth) by setting the parameter through
the python interface rather than compile the code after changing the *.cc file.
(we always had the parameter there, but still used the static 'ThePipeline::StageWidth'
instead)
-
Since StageWidth is now dynamically defined, change the interstage communication
structure to use a vector and get rid of array and array handling index (toNextStageIndex)
since we can just make calls to the list for the same information
2011-02-04 00:08:18 -05:00
Korey Sewell
8ac717ef4c inorder: multi-issue branch resolution
Only execute (resolve) one branch per cycle because handling more than one is
a little more complicated
2011-02-04 00:08:17 -05:00
Korey Sewell
be17617990 inorder: pipe. stage inst. buffering
use skidbuffer as only location for instructions between stages. before,
we had the insts queue from the prior stage and the skidbuffer for the
current stage, but that gets confusing and this consolidation helps
when handling squash cases
2011-02-04 00:08:16 -05:00
Korey Sewell
050944dd73 inorder: change skidBuffer to list instead of queue
manage insertion and deletion like a queue but will need
access to internal elements for future changes
Currently, skidbuffer manages any instruction that was
in a stage but could not complete processing, however
we will want to manage all blocked instructions (from prev stage
and from cur. stage) in just one buffer.
2011-02-04 00:08:15 -05:00
Korey Sewell
7f937e11e2 inorder: activity tracking bug
Previous code was marking CPU activity on almost every cycle due to a bug in
tracking the status of pipeline stages. This disables the CPU from sleeping
on long latency stalls and increases simulation time
2011-02-04 00:08:13 -05:00
Gabe Black
091a3e6cc0 Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
--HG--
rename : src/sim/fault.hh => src/sim/fault_fwd.hh
2011-02-03 21:47:58 -08:00
Gabe Black
fd26707731 Mem,X86: Make the IO bridge pass APIC messages back towards the CPU. 2011-02-03 20:56:27 -08:00
Gabe Black
00f24ae92c Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
2011-02-03 20:23:00 -08:00
Gabe Black
869a046e41 O3: Fix a style bug in O3. 2011-02-02 23:34:14 -08:00
Gabe Black
cb22bead7d X86: Get rid of the stupd microop. 2011-02-02 19:57:12 -08:00
Gabe Black
54f88d84c2 Stats: Update the x86 stats to reflect changing stupd to a store and update. 2011-02-02 19:56:49 -08:00
Gabe Black
eabbdbee63 X86: Replace the stupd microop with a store/update sequence. 2011-02-02 19:56:38 -08:00
Gabe Black
a7d4fa45b4 X86: Build O3 by default in SE. 2011-02-02 18:17:16 -08:00
Gabe Black
75d34c14fc Time: Add serialization functions to the Time class. 2011-02-02 18:05:03 -08:00
Gabe Black
c4b81d311e X86: Change how the default disk image gets set up.
The disk image to use was always being forced to a particular value. This
change changes what disk image is selected as the default based on the
architecture being built. In the future, a more sophisticated system might be
used that selected a path based on certain rules instead of relying on one off
file names.
2011-02-02 18:03:58 -08:00
Gabe Black
119f5f8e94 X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
2011-02-01 18:28:41 -08:00
Gabe Black
4b4cd0303e Fault: Move the definition of NoFault from faults.hh to fault.hh.
Moving the definition of NoFault into fault.hh doesn't bring any new
dependencies with it, and allows some files to include just fault.hh which has
less baggage. NoFault will still be available to everything that includes
faults.hh because it includes fault.hh.
2011-01-31 13:13:00 -08:00
Nathan Binkert
048b1e5843 refcnt: Change things around so that we handle constness correctly.
To use a non const pointer:
typedef RefCountingPtr<Foo> FooPtr;

To use a const pointer:
typedef RefCountingPtr<const Foo> ConstFooPtr;
2011-01-22 21:48:06 -08:00
Gabe Black
0e64e1be0f SConstruct: Fix the librt check in SConstruct. 2011-01-21 17:51:22 -08:00
Steve Reinhardt
5c99ae60b8 checkpointing: fix bug from curTick accessor conversion.
Regex replacement of curTick with curTick() accidentally
changed checkpoint key string for serialization but not
for unserialization.
2011-01-20 22:13:33 -08:00
Gabe Black
ddeaf1252f TimeSync: Use the new setTick and getTick functions. 2011-01-19 16:22:23 -08:00
Gabe Black
23bab6783b Time: Add setTick and getTick functions to the Time class. 2011-01-19 16:22:15 -08:00
Gabe Black
a368fba7d4 Time: Add a mechanism to prevent M5 from running faster than real time.
M5 skips over any simulated time where it doesn't have any work to do. When
the simulation is active, the time skipped is short and the work done at any
point in time is relatively substantial. If the time between events is long
and/or the work to do at each event is small, it's possible for simulated time
to pass faster than real time. When running a benchmark that can be good
because it means the simulation will finish sooner in real time. When
interacting with the real world through, for instance, a serial terminal or
bridge to a real network, this can be a problem. Human or network response time
could be greatly exagerated from the perspective of the simulation and make
simulated events happen "too soon" from an external perspective.

This change adds the capability to force the simulation to run no faster than
real time. It does so by scheduling a periodic event that checks to see if
its simulated period is shorter than its real period. If it is, it stalls the
simulation until they're equal. This is called time syncing.

A future change could add pseudo instructions which turn time syncing on and
off from within the simulation. That would allow time syncing to be used for
the interactive parts of a session but then turned off when running a
benchmark using the m5 utility program inside a script. Time syncing would
probably not happen anyway while running a benchmark because there would be
plenty of work for M5 to do, but the event overhead could be avoided.
2011-01-19 11:48:00 -08:00
Ali Saidi
f7885b8f26 ARM/O3: Add regressions for ARM w/ O3 CPU. 2011-01-18 16:30:06 -06:00