Commit graph

55 commits

Author SHA1 Message Date
Andreas Hansson
f26a289295 mem: Split port retry for all different packet classes
This patch fixes a long-standing isue with the port flow
control. Before this patch the retry mechanism was shared between all
different packet classes. As a result, a snoop response could get
stuck behind a request waiting for a retry, even if the send/recv
functions were split. This caused message-dependent deadlocks in
stress-test scenarios.

The patch splits the retry into one per packet (message) class. Thus,
sendTimingReq has a corresponding recvReqRetry, sendTimingResp has
recvRespRetry etc. Most of the changes to the code involve simply
clarifying what type of request a specific object was accepting.

The biggest change in functionality is in the cache downstream packet
queue, facing the memory. This queue was shared by requests and snoop
responses, and it is now split into two queues, each with their own
flow control, but the same physical MasterPort. These changes fixes
the previously seen deadlocks.
2015-03-02 04:00:35 -05:00
Andreas Hansson
edc77fc03c misc: Move AddrRangeList from port.hh to addr_range.hh
The new location seems like a better fit. The iterator typedefs are
removed in favour of using C++11 auto.
2014-10-16 05:49:59 -04:00
Curtis Dunham
725be98fe8 mem: Provide better diagnostic for unconnected port
When _masterPort is null, a message to that effect is
more helpful than a segfault.
2014-09-27 09:08:30 -04:00
Andreas Hansson
d4273cc9a6 mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.

Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.

A follow-on patch updates the configuration scripts accordingly.
2013-07-18 08:31:16 -04:00
Andreas Hansson
7e13c4d046 mem: Make returning snoop responses occupy response layer
This patch introduces a mirrored internal snoop port to facilitate
easy addition of flow control for the snoop responses that are turned
into normal responses on their return. To perform this, the slave
ports of the coherent bus are wrapped in internal master ports that
are passed as the source ports to the response layer in question.

As a result of this patch, there is more contention for the response
resources, and as such system performance will decrease slightly.

A consequence of the mirrored internal port is that the port the bus
tells to retry (the internal one) and the port actually retrying (the
mirrored) one are not the same. Thus, the existing check in tryTiming
is not longer correct. In fact, the test is redundant as the layer is
only in the retry state while calling sendRetry on the waiting port,
and if the latter does not immediately call the bus then the retry
state is left. Consequently the check is removed.
2013-05-30 12:54:02 -04:00
Andreas Hansson
3d98119717 mem: Fix typo in port comments
This patch merely fixes a few typos in the port comments.
2012-10-31 09:28:23 -04:00
Andreas Hansson
2a740aa096 Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.

The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
2012-10-15 08:12:35 -04:00
Andreas Hansson
ffb6aec603 AddrRange: Transition from Range<T> to AddrRange
This patch takes the final plunge and transitions from the templated
Range class to the more specific AddrRange. In doing so it changes the
obvious Range<Addr> to AddrRange, and also bumps the range_map to be
AddrRangeMap.

In addition to the obvious changes, including the removal of redundant
includes, this patch also does some house keeping in preparing for the
introduction of address interleaving support in the ranges. The Range
class is also stripped of all the functionality that is never used.

--HG--
rename : src/base/range.hh => src/base/addr_range.hh
rename : src/base/range_map.hh => src/base/addr_range_map.hh
2012-09-19 06:15:44 -04:00
Andreas Hansson
d14e5857c7 Port: Stricter port bind/unbind semantics
This patch tightens up the semantics around port binding and checks
that the ports that are being bound are currently not connected, and
similarly connected before unbind is called.

The patch consequently also changes the order of the unbind and bind
for the switching of CPUs to ensure that the rules are adhered
to. Previously the ports would be "over-written" without any check.

There are no changes in behaviour due to this patch, and the only
place where the unbind functionality is used is in the CPU.
2012-08-28 14:30:27 -04:00
Anthony Gutierrez
0b3897fc90 O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.

This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
2012-08-15 10:38:08 -04:00
Andreas Hansson
46d9adb68c Port: Make getAddrRanges const
This patch makes getAddrRanges const throughout the code base. There
is no reason why it should not be, and making it const prevents adding
any unintentional side-effects.
2012-07-09 12:35:34 -04:00
Andreas Hansson
830391cad9 Port: Add getAddrRanges to master port (asking slave port)
This patch adds getAddrRanges to the master port, and thus avoids
going through getSlavePort to be able to ask the slave. Similar to the
previous patch that added isSnooping to the SlavePort, this patch aims
to introduce an additional level of hierarchy in the ports (base port
being protocol-agnostic) and getSlave/MasterPort will return port
pointers to these base classes.

The function is named getAddrRanges also on the master port, but does
nothing besides asking the connected slave port. The slave port, as
before, has to provide an implementation and actually produce a list
of address ranges. The initial design used the name getSlaveAddrRanges
for the new function, but the more verbose name was later changed.
2012-07-09 12:35:33 -04:00
Andreas Hansson
49407d76aa Port: Add isSnooping to slave port (asking master port)
This patch adds isSnooping to the slave port, and thus avoids going
through getMasterPort to be able to ask the master. Over the course of
the next few patches, all getMasterPort/getSlavePort in Port and
MemObject are to be protocol agnostic, and the snooping is part of the
protocol layer.

The function is already present on the master port, where it is
implemented by the module itself, e.g. a cache. On the slave side, it
is merely asking the connected master port. The same name is used by
both functions despite their difference in behaviour. The initial
design used isMasterSnooping on the slave port side, but the more
verbose function name was later changed.
2012-07-09 12:35:32 -04:00
Andreas Hansson
17f9270dad Port: Move retry from port base class to Master/SlavePort
This patch is the last part of moving all protocol-related
functionality out of the Port base class. All the send/recv functions
are already moved, and the retry (which still governs all the timing
transport functions) is the only part that remained in the base class.

The only point where this currently causes a bit of inconvenience is
in the bus where the retry list is global and holds Port pointers (not
Master/SlavePort). This is about to change with the split into a
request/response bus and will soon be removed anyway.

The patch has no impact on any regressions.
2012-07-09 12:35:31 -04:00
Andreas Hansson
cad802761a Packet: Unify the use of PortID in packet and port
This patch removes the Packet::NodeID typedef and unifies it with the
Port::PortId. The src and dest fields in the packet are used to hold a
port id (e.g. in the bus), and thus the two should actually be the
same.

The typedef PortID is now global (in base/types.hh) and aligned with
the ThreadID in terms of capitalisation and naming of the
InvalidPortID constant.

Before this patch, two flags were used for valid destination and
source, rather than relying on a named value (InvalidPortID), and
this is now redundant, as the src and dest field themselves are
sufficient to tell whether the current value is a valid port
identifier or not. Consequently, the VALID_SRC and VALID_DST are
removed.

As part of the cleaning up, a number of int parameters and local
variables are updated to use PortID.

Note that Ruby still has its own NodeID typedef. Furthermore, the
MemObject getMaster/SlavePort still has an int idx parameter with a
default value of -1 which should eventually change to PortID idx =
InvalidPortID.
2012-05-30 05:29:42 -04:00
Andreas Hansson
3fea59e162 MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.

For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).

The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.

With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 13:40:42 -04:00
Andreas Hansson
4c92708b48 MEM: Add the PortId type and a corresponding id field to Port
This patch introduces the PortId type, moves the definition of
INVALID_PORT_ID to the Port class, and also gives every port an id to
reflect the fact that each element in a vector port has an
identifier/index.

Previously the bus and Ruby testers (and potentially other users of
the vector ports) added the id field in their port subclasses, and now
this functionality is always present as it is moved to the base class.
2012-04-25 10:41:23 -04:00
Andreas Hansson
dccca0d3a9 MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.

Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.

Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.

Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.

The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.

In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 05:45:07 -04:00
William Wang
f9d403a7b9 MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 09:40:11 -04:00
Andreas Hansson
485d103255 MEM: Move all read/write blob functions from Port to PortProxy
This patch moves the readBlob/writeBlob/memsetBlob from the Port class
to the PortProxy class, thus making a clear separation of the basic
port functionality (recv/send functional/atomic/timing), and the
higher-level functional accessors available on the port proxies.

There are only a few places in the code base where the blob functions
were used on ports, and they are all for peeking into the memory
system without making a normal memory access (in the memtest, and the
malta and tsunami pchip). The memtest also exemplifies how easy it is
to create a non-translating proxy if desired. The malta and tsunami
pchip used a slave port to perform a functional read, and this is now
changed to rely on the physProxy of the system (to which they already
have a pointer).
2012-02-24 11:46:39 -05:00
Andreas Hansson
07cf9d914b MEM: Separate queries for snooping and address ranges
This patch simplifies the address-range determination mechanism and
also unifies the naming across ports and devices. It further splits
the queries for determining if a port is snooping and what address
ranges it responds to (aiming towards a separation of
cache-maintenance ports and pure memory-mapped ports). Default
behaviours are such that most ports do not have to define isSnooping,
and master ports need not implement getAddrRanges.
2012-01-17 12:55:09 -06:00
Andreas Hansson
142380a373 MEM: Remove Port removeConn and MemObject deletePortRefs
Cleaning up and simplifying the ports and going towards a more strict
elaboration-time creation and binding of the ports.
2012-01-17 12:55:09 -06:00
Andreas Hansson
6315e5bbb5 MEM: Remove the notion of the default port
This patch removes the default port and instead relies on the peer
being set to NULL initially. The binding check (i.e. is a port
connected or not) will eventually be moved to the init function of the
modules.
2012-01-17 12:55:09 -06:00
Andreas Hansson
de34e49d15 MEM: Simplify ports by removing EventManager
This patch removes the inheritance of EventManager from the ports and
moves all responsibility for event queues to the owner. Eventually the
event manager should be the interface block, which could either be the
structural owner or a subblock like a LSQ in the O3 CPU for example.
2012-01-17 12:55:09 -06:00
Andreas Hansson
f85286b3de MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Nathan Binkert
6faf377b53 types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
Nathan Binkert
709d859530 includes: use base/types.hh not inttypes.h or stdint.h 2009-05-17 14:34:51 -07:00
Nathan Binkert
8291d9db0a eventq: Major API change for the Event and EventQueue structures.
Since the early days of M5, an event needed to know which event queue
it was on, and that data was required at the time of construction of
the event object.  In the future parallelized M5, this sort of
requirement does not work well since the proper event queue will not
always be known at the time of construction of an event.  Now, events
are created, and the EventQueue itself has the schedule function,
e.g. eventq->schedule(event, when).  To simplify the syntax, I created
a class called EventManager which holds a pointer to an EventQueue and
provides the schedule interface that is a proxy for the EventQueue.
The intent is that objects that frequently schedule events can be
derived from EventManager and then they have the schedule interface.
SimObject and Port are examples of objects that will become
EventManagers.  The end result is that any SimObject can just call
schedule(event, when) and it will just call that SimObject's
eventq->schedule function.  Of course, some objects may have more than
one EventQueue, so this interface might not be perfect for those, but
they should be relatively few.
2008-10-09 04:58:23 -07:00
Steve Reinhardt
caaac16803 Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Steve Reinhardt
6b45238316 Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
2008-06-21 01:04:43 -04:00
Nathan Binkert
e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Steve Reinhardt
3952e41ab1 Add functional PrintReq command for memory-system debugging.
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2008-01-02 12:20:15 -08:00
Gabe Black
8a020d40d3 Make ports that aren't connected to anything fail more gracefully.
--HG--
extra : convert_revision : 3803b28fb2fdfd729f01f1a44df2ae02ef83a2fc
2007-11-28 14:39:19 -08:00
Steve Reinhardt
41241799ae Change getDeviceAddressRanges to use bool for snoop arg.
--HG--
extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-21 23:36:09 -07:00
Ali Saidi
0dfc29a023 fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
    fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
    fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
    by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
2007-05-07 14:42:03 -04:00
Kevin Lim
ad44834907 Two fixes:
1. Make sure connectMemPorts() only gets called when the CPU's peer gets changed.  This is done by making setPeer() virtual, and overriding it in the CPU's ports.  When it gets called on a CPU's port (dcache specifically), it calls the normal setPeer() function, and also connectMemPorts().
2. Consolidate redundant code that handles switching in a CPU.

src/cpu/base.cc:
    Move common code of switching over peers to base CPU.
src/cpu/base.hh:
    Move common code of switching over peers to BaseCPU.
src/cpu/o3/cpu.cc:
    Add in function that updates thread context's ports.
    Also use updated function to takeOverFrom() in BaseCPU.  This gets rid of some repeated code.
src/cpu/o3/cpu.hh:
    Include function to update thread context's memory ports.
src/cpu/o3/lsq.hh:
    Add function to dcache port that will update the memory ports upon getting a new peer.
    Also include a function that will tell the CPU to update those memory ports.
src/cpu/o3/lsq_impl.hh:
    Add function that will update the memory ports upon getting a new peer.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Add function that will update thread context's memory ports upon getting a new peer.
    Also use the new BaseCPU's take over from function.
src/cpu/simple/atomic.hh:
    Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer.
src/cpu/simple/timing.hh:
    Add function that will update thread context's memory ports upon getting a new peer.
src/mem/port.hh:
    Make setPeer virtual so that other classes can override it.

--HG--
extra : convert_revision : 2050f1241dd2e83875d281cfc5ad5c6c8705fdaf
2007-03-09 10:06:09 -05:00
Ali Saidi
027dfa01e6 stop m5 from leaking like a sieve
don't create a new physPort/virtPort every time activateContext() is called
add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs()
on the port owner as well as delete it's peer
still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic

src/cpu/thread_state.cc:
    if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it
src/mem/bus.cc:
src/mem/bus.hh:
    add ability to delete a port by usig a hash_map instead of an array to store port ids
    add a function to do deleting
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/mem_object.cc:
src/mem/mem_object.hh:
    adda function to delete port references from a memory object
src/mem/port.cc:
src/mem/port.hh:
    add a removeConn function that tell the owener to delete any references to the port and then deletes its peer

--HG--
extra : convert_revision : 272f0c8f80e1cf1ab1750d8be5a6c9aa110b06a4
2007-03-08 18:57:15 -05:00
Steve Reinhardt
997fc505a8 Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.

--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-07 10:53:37 -08:00
Ali Saidi
63fdabf191 make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
    Add code to detect compiler and choose cflags based on detected compiler
    Fix zlib check to work with suncc
src/SConscript:
    split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
    use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
    add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
    use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
    include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
    remove dangling comma
src/arch/sparc/system.cc:
    dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
    use std namespace for string ops
src/arch/sparc/utility.hh:
    no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
    dummy returns to for suncc front end
src/base/cprintf.hh:
    use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
    don't need to define hash for suncc
src/base/hostinfo.cc:
    need stdio.h for sprintf
src/base/loader/object_file.cc:
    munmap is in std namespace not null
src/base/misc.hh:
    use M5 generic noreturn macros
    use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
    we need file.h for file flags
src/base/random.cc:
    mess with include files to make suncc happy
src/base/remote_gdb.cc:
    malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
    use std namespace for floor
src/base/stats/text.cc:
    include math.h for rint (cmath won't work)
src/base/time.cc:
    use suncc version of ctime_r
src/base/time.hh:
    change macro to work with both gcc and suncc
src/base/timebuf.hh:
    include cstring from memset and use std::
src/base/trace.hh:
    change variadic macros to be normal format
src/cpu/SConscript:
    add dummy returns where appropriate
src/cpu/activity.cc:
    include cstring for memset
src/cpu/exetrace.hh:
    include cstring fro memcpy
src/cpu/simple/base.hh:
    add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
    add dummy return where appropriate
src/dev/ide_atareg.h:
    make define work for both gnuc and suncc
src/dev/io_device.hh:
    add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
    include cstring for string ops
src/dev/sparc/mm_disk.cc:
    add dummy return where appropriate
    include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
    Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
    cast hastSets to double for log() call
src/mem/physical.cc:
    cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
    make define work for suncc and gnuc

--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-26 18:48:51 -05:00
Kevin Lim
b26355daa8 Ports now have a pointer to the MemObject that owns it (can be NULL).
src/cpu/simple/atomic.hh:
    Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
    Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
    Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
    Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
    Ports now optionally take in the MemObject that owns it.

--HG--
extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-31 13:59:30 -05:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-20 00:10:12 -07:00
Ron Dreslinski
1345183a89 Move away from using the statusChange function on snoops. Clean up snooping code in general.
--HG--
extra : convert_revision : 5a57bfd7742a212047fc32e8cae0dc602fdc915c
2006-10-08 18:48:03 -04:00
Steve Reinhardt
f9ae0dcf10 Move more common functionality into SimpleTimingPort,
allowing derived classes to be simplified.

--HG--
extra : convert_revision : c980d3aec5e6c044d8f41e96252726fe9a256605
2006-08-30 16:24:26 -07:00
Ron Dreslinski
9f18764441 Commiting a version of the multi-phase snoop atomic bus so people can see the framework. Doesn't work, but also doesn't break uni-processor systems.
Working on pulling out the changes in the cache so that it remains working.

src/mem/bus.cc:
    Changes for multi-phase snoop
    Some code for registering snoop ranges (a version that compiles and runs, but does nothing)
src/mem/bus.hh:
    Changes for multi-phase snoop
src/mem/packet.hh:
    Flag for multi-phase snoop
src/mem/port.hh:
    Status for multi-phase snoop

--HG--
extra : convert_revision : 4c2e5263bba16e3bcf03aabe36ff45ec36de4720
2006-08-22 16:08:18 -04:00
Steve Reinhardt
5bd07f98ed Fix up doxygen.
--HG--
rename : docs/footer.html => src/doxygen/footer.html
rename : docs/stl.hh => src/doxygen/stl.hh
extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
2006-08-14 19:25:07 -04:00
Kevin Lim
f1a24337a8 Allow ports to be created without a name.
--HG--
extra : convert_revision : 26dad6853feaf4f68907aab902c54259281cac1c
2006-06-25 00:24:50 -04:00
Ali Saidi
8ee856f1d5 add write/read functions that have endian conversions in them
when we get a virtual port delete it (even though delete does nothing in these cases)

src/arch/alpha/linux/system.cc:
src/arch/alpha/stacktrace.cc:
src/base/remote_gdb.cc:
src/cpu/simple_thread.cc:
    when we get a virtual port delete it (even though delete does nothing in this case)
src/mem/port.hh:
src/mem/vport.hh:
    add write/read functions that have endian conversions in them

--HG--
extra : convert_revision : 163e05cc038c461f95c92f8ce55422033f9ea513
2006-06-08 19:03:58 -04:00
Ali Saidi
cb0cf2dd8a Updated Authors from bk prs info
--HG--
extra : convert_revision : 77f475b156d81c03a2811818fa23593d5615c685
2006-05-31 19:26:56 -04:00
Steve Reinhardt
91e3aa6295 Minor further cleanup & commenting of Packet class.
src/cpu/simple/atomic.cc:
    Make common ifetch setup based on Request rather than Packet.
    Packet::reset() no longer a separate function.
    sendAtomic() returns latency, not absolute tick.
src/cpu/simple/atomic.hh:
    sendAtomic returns latency, not absolute tick.
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    Make common ifetch setup based on Request rather than Packet.
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/physical.cc:
    Get rid of redundant Packet time field.
src/mem/packet.cc:
    Eliminate reset() method.
src/mem/packet.hh:
    Fold reset() function into reinitFromRequest()... it was
    only ever called together with that function.
    Get rid of redundant time field.
    Cleanup/add comments.
src/mem/port.hh:
    Document in comment that sendAtomic returns latency, not absolute tick.

--HG--
extra : convert_revision : 0252f1a294043ca3ed58f437232ad24fc0733e0c
2006-05-30 22:30:42 -04:00
Steve Reinhardt
0e5db091e9 Fix Port pointer initialization.
src/mem/port.hh:
    Initialize peer port pointer to NULL.
    Move private data members together.

--HG--
extra : convert_revision : dab01f81f0934758891a6b6dc2ad5328149d164b
2006-05-30 19:49:28 -04:00