This patch fixes a bug in etherswitch. When a packet gets inserted
in the output fifo, the txEvent has to always be reschedule,
not only when an event is already scheduled. This can raise
the assertion in the reschedule function.
Don't consult the TLB test interface for PA's returned by functional
translations by the AT instruction. We implement this by chaning the
ISA code to synthesize 0-length functional reads for the TLB lookup.
The TLB then bypasses the final PA check in the tester if the size is
zero.
Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
The ELF loader currently has an assertion that checks if the size of a
loaded .text secion is non-zero. This is useful in the general case as
an empty text section normally indicates that there is something
strange with the ELF file. However, asserting isn't very useful. This
changeset converts the assert into a warning that tells the user that
something strange is happening.
Change-Id: I313e17847b50a0eca00f6bd00a54c610d626c0f0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Currently garnet will not run due to double statistic registration of new
stats in ClockedObject. This occurs because a temporary array named 'cls'
is being added as a child to garnet internal and external link SimObjects.
This patch simply renames the temporary array which prevents it from
being added as a child object and avoids the assertion that a statistic
was already registered.
Committed by Jason Lowe-Power <jason@lowepower.com>
Sync DRAMPower to external tool
This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am a maintainer.
The version used is the commit:
902a00a1797c48a9df97ec88868f20e847680ae6
from 07. May. 2016.
Committed by Jason Lowe-Power <jason@lowepower.com>
This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.
Committed by Jason Lowe-Power <jason@lowepower.com>
This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.
Committed by Jason Lowe-Power <jason@lowepower.com>
In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.
Highlights
1- It explores 3 different HMC architectures
2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This will connect vaults to serial links
3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports
4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink
Committed by Jason Lowe-Power <jason@lowepower.com>
The style checker for spacing around control statements (ControlSpace)
and the whitespace checker (Whitespace) didn't refer to some of their
configuration variables correctly. This changeset fixes those issues.
Reported-by: Jason Lowe-Power <power.jg@gmail.com>
--HG--
extra : amend_source : 05d82d27d4c42aacd78b514d3ca35ca5744164bb
In previous versions of systemC-gem5 coupling statistics were not updated
for the systemc-gem5 simulation. systemC-gem5 simulation only need the
previously built config.ini file and normal gem5 simulation has to be run
once to generate config.ini file. Thus stats.txt inside the m5out folder is
redundant for systemC-gem5 simulation. A new stats file is now generated
with the all the statistics for systemC-gem5 simulation. This will also
resolve the stats issue in tlm-sysmtemC simulation.
Committed by Jason Lowe-Power <jason@lowepower.com>
This patch changes how the embedded swig code is loaded to ensure that
gem5 works with swig 3.0.9. For Python 2.7 and above, swig 3.0.9 now
relies on importlib, and actually looks in the appropriate packages,
even for the wrapped C code. However, the swig wrapper does not
explicitly place the module in the right package (it just calls
Py_InitModule), and we have to take explicit action to ensure that the
swig code can be loaded. This patch adds the information to the
generated wrappers and the appropriate calls to set the context as
part of the swig initialisation.
Previous versions of swig used to fall back on looking in the global
namespace for the wrappers (and still do for Python 2.6), but
technically things should not work without the functionality in this
patch.
Previously when we initialized the TLB we would allocate a number of
TLB entries which would be marked as valid. As a result the TLB
contained an entry which would be considered a valid entry for the 0
page.
Change-Id: I23ace86426a171a4f6200ebeb29ad57c21647036
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
The use of array tuples, requires an explicit include of the array library
Change-Id: I06730051777a97edf80e41a5604184b387b12239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
The snoop filter handles requests in two steps which preceed and
follow the call to send the packet downstream. An address mapper could
possibly change the address of the packet when it is sent downstream
breaking the snoop filter assumption that the address is unchanged
Change-Id: Ib2db755e9ebef4f2f7c0169a46b1b11185ffbe79
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Add a "test" command to tests.py that queries a test pickle file and
returns different exit codes depending on the outcome of the tests in
the file. The following exit codes can currently be returned:
* 0: All tests were successful or skipped.
* 1: General fault in the script such as incorrect parameters or
failing to parse a pickle file.
* 2: At least one test failed to run. This is what the summary
formatter usually shows as a 'FAILED'.
* 3: All tests ran correctly, but at least one failed to verify
its output. When displaying test output using the summary
formatter, such a test would show up as 'CHANGED'.
The command can be invoked like this:
./tests/tests.py test `find build/ARM/tests/opt/ -name status.pickle`
Change-Id: I7e6bc661516f38ff08dfda7c4359a1e10bf97864
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
The test base class already assumes that test cases consists of a run
stage and a verification stage. Reflect this in the results class to
make it possible to detect cases where a run was successful, but
didn't verify.
Change-Id: I31ef393e496671221c5408aca41649cd8dda74ca
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
The traffic generator currently resolves relative trace paths relative
to gem5's current working directory. This can lead to surprising
results for relative paths where the expectation would normally be
that they are resolved relative to the configuration file. This
changeset implements config-relative trace file lookups. The old
behavior is kept as a fallback for configs that expect that behavior.
Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
This patch ensures a walker cache is instantiated if specfied.
Change-Id: I2c6b4bf3454d56bb19558c73b406e1875acbd986
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Add helper functions to dump the guest kernel's dmesg buffer to a text
file in m5out. This functionality is split into two parts. First, a
dmesg dump function that can be used in other places:
void Linux::dumpDmesg(ThreadContext *, std::ostream &)
This function is used to implement two PCEvents: DmesgDumpEvent and
KernelPanic event. The only difference between the two is that the
latter produces a gem5 panic instead of a warning in addition to
dumping the kernel log.
Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
The SymbolTable class currently assumes that at most one symbol can
point to a given address. If multiple symbols point to the same
address, only the first one gets added to the internal symbol table
since there is already a match in the address table.
This changeset converts the address table from a map into a multimap
to be able to handle cases where an address maps to multiple
symbols. Additionally, the insert method is changed to not fail if
there is a match in the address table.
Change-Id: I6b4f1d5560c21e49a4af33220efb2a8302961768
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
There is a mismatch between DataType and SrcDataType in constructing
Atomic ST instruction. The mismatch causes atomic_store and
atomic_store_explicit function to store incorrect value in memory.
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work
items); replaced it with a parameter in the GPU.py configuration script.
Changed all data structures dependent on the Wavefront size to be dynamically
sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at
initialization time.
This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations
Committed by Jason Lowe-Power <power.jg@gmail.com>
mathexpr.hh uses std::function<> but was not including the appropriate
header, which resulted in an error
build/ARM/sim/mathexpr.hh:51:18: error: 'function' in namespace 'std'
does not name a template type
typedef std::function<double(std::string)> EvalCallback;
This commit adds the missing include.
Change-Id: I6c01d77d4354c6de838538f137a38f75f9866166
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
A lot of objects seem to request no-op power transitions which
currently results in large amounts of warnings. These warnings are
benign and risk hiding more serious warnings. Make the warning a
warn_once to prevent console flooding.
Change-Id: I86c74b4224b167f14469250ef86ab69fde7a227e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
This patch makes thermal models use the power figures
calculated by power models. Since there is a circular
dependency between power and thermal (and thermal was
pushed before) this patch closes that loop.
Change-Id: I8bd5acf6a5026fdbbcfac47e33d27397f24a6f7d
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
This patch adds some basic support for power models in gem5.
The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.
The model allows it to be extended to use other kinds of models.
Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
Add functionality to the BaseCPU that will put the entire CPU
into a low-power idle state whenever all threads in it are idle.
Change-Id: I984d1656eb0a4863c87ceacd773d2d10de5cfd2b
The power stats are currently very noisy even if no power model has
been loaded. Silence stats that are either zero or nan.
Change-Id: I7d0220c2fcf01131084a219228f140cfaddaf95b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Add 4 power states to the ClockedObject, provides necessary access
functions to check and update the power state. Default power state
is UNDEFINED, it is responsibility of the respective simulation
model to provide the startup state and any other logic for state
change. Add number of transition stat. Add distribution of time
spent in clock gated state. Add power state residency stat. Add
dump call back function to allow stats update of distribution
and residency stats.
Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).
Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
We want to extend the stats of objects hierarchically and thus it is necessary
to register the statistics of the base-class(es), as well. For now, these are
empty, but generic stats will be added there.
Patch originally provided by Akash Bagdia at ARM Ltd.
This implements SwapReq for Ruby memory.
A SwapReq should be treated like a write, except that the response
packet contains the overwritten data.
Note that, in particular, the conditional checking for isStore/isLoad
needs to be reversed, as a SwapReq is both.
In particular, when EL0 is in AArch32 but EL1 is AArch64, AArch64
memory translation must be used. This is essential for typical
AArch64/32 interworking use cases.
The traffic generator tests currently assume that they are run from
the root of the source directory. This sometimes breaks tests when
they are run using the new test framework.
Change-Id: I6538a7902694c5d2c980295e076ea1c09acc4291
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
The ERET instruction doesn't set PSTATE correctly in some cases
(particularly when returning to aarch32 code). Among other things,
this breaks EL0 thumb code when using a 64-bit kernel. This changeset
updates the ERET implementation to match the ARM ARM.
Change-Id: I408e7c69a23cce437859313dfe84e68744b07c98
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1
and higher are all 32-bit. This breaks interprocessing since an
aarch64 EL1 uses different enable/disable bits. This change updates
the permission checks to according to what is prescribed by the ARM
ARM.
Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
