Commit graph

54 commits

Author SHA1 Message Date
Uri Wiener
a8fbfefb5e mem: Adding verbose debug output in the memory system
This patch provides useful printouts throughut the memory system. This
includes pretty-printed cache tags and function call messages
(call-stack like).
2013-04-22 13:20:33 -04:00
Andreas Hansson
0622f30961 mem: Add predecessor to SenderState base class
This patch adds a predecessor field to the SenderState base class to
make the process of linking them up more uniform, and enable a
traversal of the stack without knowing the specific type of the
subclasses.

There are a number of simplifications done as part of changing the
SenderState, particularly in the RubyTest.
2013-02-19 05:56:05 -05:00
Andreas Hansson
c60db56741 Packet: Remove NACKs from packet and its use in endpoints
This patch removes the NACK frrom the packet as there is no longer any
module in the system that issues them (the bridge was the only one and
the previous patch removes that).

The handling of NACKs was mostly avoided throughout the code base, by
using e.g. panic or assert false, but in a few locations the NACKs
were actually dealt with (although NACKs never occured in any of the
regressions). Most notably, the DMA port will now never receive a NACK
and the backoff time is thus never changed. As a consequence, the
entire backoff mechanism (similar to a PCI bus) is now removed and the
DMA port entirely relies on the bus performing the arbitration and
issuing a retry when appropriate. This is more in line with e.g. PCIe.

Surprisingly, this patch has no impact on any of the regressions. As
mentioned in the patch that removes the NACK from the bridge, a
follow-up patch should change the request and response buffer size for
at least one regression to also verify that the system behaves as
expected when the bridge fills up.
2012-08-22 11:39:59 -04:00
Andreas Hansson
3e0ed08706 Packet: Cleaning up packet command and attribute
This patch removes unused commands and attributes from the packet to
avoid any confusion. It is part of an effort to clear up how and where
different commands and attributes are used.
2012-05-23 09:18:04 -04:00
Nilay Vaish
9481d05b8a MemCmd: Add a command for invalidation requests to LSQ
This command will be sent from the memory system (Ruby) to the LSQ of
an O3 CPU so that the LSQ, if it needs to, invalidates the address in
the request packet.
2012-01-23 11:07:11 -06:00
Ali Saidi
c40ae2c3fb Packet: Put back part of the assert 2012-01-11 19:27:11 -05:00
Ali Saidi
bc1c21274e Packet: Remove meaningless assert statement 2012-01-11 19:24:13 -05:00
Geoffrey Blake
e826d23a2e Packet: Add derived class FunctionalPacket to enable partial functional reads
This adds the derived class FunctionalPacket to fix a long standing
deficiency in the Packet class where it was unable to handle finding data to
partially satisfy a functional access.  Made this a derived class as
functional accesses are used only in certain contexts and to not add any
additional overhead to the existing Packet class.
2012-01-09 18:10:05 -06:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Nathan Binkert
39a055645f includes: sort all includes 2011-04-15 10:44:06 -07:00
Somayeh Sardashti
c8bbfed937 This patch supports cache flushing in MOESI_hammer 2011-03-28 10:49:45 -05:00
Steve Reinhardt
1249728494 cache: fail SC when invalidated while waiting for bus
Corrects an oversight in cset f97b62be544f.  The fix there only
failed queued SCUpgradeReq packets that encountered an
invalidation, which meant that the upgrade had to reach the L2
cache.  To handle pending requests in the L1 we must similarly
fail StoreCondReq packets too.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
6dc599ea9b mem: fix functional accesses to deal with coherence change
We can't just obliviously return the first valid cache block
we find any more... see comments for details.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
62c06c1403 mem: fix dumb typo in copyrights 2010-08-25 14:08:27 -07:00
Steve Reinhardt
f24ae2ec2a cache: fail store conditionals when upgrade loses race
Requires new "SCUpgradeReq" message that marks upgrades
for store conditionals, so downstream caches can fail
these when they run into invalidations.
See http://www.m5sim.org/flyspray/task/197
2010-06-16 15:25:57 -07:00
Gabe Black
3e5f487663 Memory: Rename LOCKED for load locked store conditional to LLSC. 2009-04-19 04:25:01 -07:00
Gabe Black
3031af21c7 X86: Fix the flags for interrupt response messages. 2009-04-19 03:53:29 -07:00
Nathan Binkert
3535d746ab style: clean up the Packet stuff 2008-11-10 11:51:17 -08:00
Gabe Black
e459013182 Create a message port for sending messages as apposed to reading/writing a memory range. 2008-10-12 12:08:51 -07:00
Steve Reinhardt
8e7ddce284 Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. 2008-07-15 14:38:51 -04:00
Steve Reinhardt
6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02 15:22:38 -08:00
Steve Reinhardt
3952e41ab1 Add functional PrintReq command for memory-system debugging.
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2008-01-02 12:20:15 -08:00
Gabe Black
7227ab5f22 Merge with head
--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-26 21:45:40 -07:00
Steve Reinhardt
8705b0799b packet: get rid of unused intersect() function.
--HG--
extra : convert_revision : f0a2947ccc49e0d18bc17a59371fa396d9ebd6c0
2007-07-27 12:46:55 -07:00
Steve Reinhardt
e9c04dad60 Fix a couple LL/SC bugs that only affected timing mode.
src/cpu/simple/timing.cc:
    Fix swap/stq_c command bug.
src/mem/packet.cc:
    Fix incorrect LoadLockedReq command response field.

--HG--
extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
2007-07-02 09:26:36 -07:00
Steve Reinhardt
d10a843723 Get rid of obsolete fixPacket() functions.
Handled by Packet::checkFunctional() now.

--HG--
extra : convert_revision : 63642254e2789c80a369ac269f317ec054ffe3c0
2007-06-30 17:51:29 -07:00
Steve Reinhardt
6ab53415ef Get rid of Packet result field. Error responses are
now encoded in cmd field.

--HG--
extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-30 10:16:18 -07:00
Steve Reinhardt
83af0fdcf5 Getting closer...
configs/example/memtest.py:
    Add progress interval option.
src/base/traceflags.py:
    Add MemTest flag.
src/cpu/memtest/memtest.cc:
    Clean up tracing.
src/cpu/memtest/memtest.hh:
    Get rid of unused code.

--HG--
extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-21 11:59:17 -07:00
Steve Reinhardt
35cf19d441 More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.

configs/example/memtest.py:
    Revamp options.
src/cpu/memtest/memtest.cc:
    No need for memory initialization.
    No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
    MemTest really doesn't want to snoop.
src/mem/bridge.cc:
    checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
    More major reorg.  Seems to work for atomic mode now,
    timing mode still broken.

--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-17 17:27:53 -07:00
Steve Reinhardt
05915ed6f7 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 6f462916cb0eb309b6799e94fbf07629abb50eba
2007-05-28 08:13:40 -07:00
Steve Reinhardt
04ac944920 Reformat comments to meet line length restriction.
--HG--
extra : convert_revision : 24c00ec4904d9fb4d6e39521e0ff8b8f60d60f6a
2007-05-28 08:04:33 -07:00
Steve Reinhardt
9048c695a0 Another pass of minor changes in preparation for new protocol.
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
    Get rid of old invalidate propagation logic in preparation
    for new multilevel snoop protocol.
src/mem/cache/coherence/coherence_protocol.cc:
    L2 cache now has protocol, so protocol must handle ReadExReq
    coming in from the CPU side.
src/mem/cache/miss/mshr_queue.cc:
    Assertion is failing, so let's take it out for now.
src/mem/packet.cc:
src/mem/packet.hh:
    Add WritebackAck command.
    Reorganize enum to put responses next to corresponding requests.
    Get rid of unused WriteReqNoAck.

--HG--
extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73
2007-05-22 06:29:48 -07:00
Ali Saidi
0dfc29a023 fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
    fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
    fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
    by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
2007-05-07 14:42:03 -04:00
Ali Saidi
b5a4d95811 rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
    add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
    Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
    Make atomic memory ops atomic
    Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
    add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
    remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
    swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
    add a post access code block
src/arch/sparc/isa/includes.isa:
    need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
    add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    add support for twinloads
    add support for swap and conditional swap instructions
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
    Add support for atomic swap memory commands
src/mem/packet_access.hh:
    Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
    Add support for atomic swap memory commands
    Rename sc code to extradata

--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2007-02-12 13:06:30 -05:00
Steve Reinhardt
997fc505a8 Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.

--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-07 10:53:37 -08:00
Steve Reinhardt
23d970e6b9 More DPRINTF cleanup.
--HG--
extra : convert_revision : db89cea42b46476d19333038522a6c144eafdab1
2007-02-06 23:53:48 -08:00
Ali Saidi
63fdabf191 make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
    Add code to detect compiler and choose cflags based on detected compiler
    Fix zlib check to work with suncc
src/SConscript:
    split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
    use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
    add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
    use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
    include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
    remove dangling comma
src/arch/sparc/system.cc:
    dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
    use std namespace for string ops
src/arch/sparc/utility.hh:
    no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
    dummy returns to for suncc front end
src/base/cprintf.hh:
    use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
    don't need to define hash for suncc
src/base/hostinfo.cc:
    need stdio.h for sprintf
src/base/loader/object_file.cc:
    munmap is in std namespace not null
src/base/misc.hh:
    use M5 generic noreturn macros
    use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
    we need file.h for file flags
src/base/random.cc:
    mess with include files to make suncc happy
src/base/remote_gdb.cc:
    malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
    use std namespace for floor
src/base/stats/text.cc:
    include math.h for rint (cmath won't work)
src/base/time.cc:
    use suncc version of ctime_r
src/base/time.hh:
    change macro to work with both gcc and suncc
src/base/timebuf.hh:
    include cstring from memset and use std::
src/base/trace.hh:
    change variadic macros to be normal format
src/cpu/SConscript:
    add dummy returns where appropriate
src/cpu/activity.cc:
    include cstring for memset
src/cpu/exetrace.hh:
    include cstring fro memcpy
src/cpu/simple/base.hh:
    add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
    add dummy return where appropriate
src/dev/ide_atareg.h:
    make define work for both gnuc and suncc
src/dev/io_device.hh:
    add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
    include cstring for string ops
src/dev/sparc/mm_disk.cc:
    add dummy return where appropriate
    include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
    Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
    cast hastSets to double for log() call
src/mem/physical.cc:
    cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
    make define work for suncc and gnuc

--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-26 18:48:51 -05:00
Ron Dreslinski
c577665040 Fix functional access errors related to delayed respnoses in cachePort
src/mem/cache/base_cache.cc:
    On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
    Create a wrapper to toggle the hasData flag on delayed responses

--HG--
extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
2006-11-12 06:35:39 -05:00
Ron Dreslinski
9a6e896d3b Big fix for functional access, where we forgot to copy the last byte on write intersections.
src/mem/packet.cc:
    Make sure to copy the whole data (we were one byte short)
src/mem/tport.cc:
    Fix for the proper semantics of fixPacket

--HG--
extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8
2006-11-10 22:41:21 -05:00
Ron Dreslinski
eda7148af2 Fix fixPacket functionality to calculate sizes properly
src/mem/packet.cc:
    Copy size is calculated by END-BEGIN not BEGIN-END

--HG--
extra : convert_revision : 0e2725c5551f8f70ff05cb285e0822afc0bb3f87
2006-10-25 14:14:37 -04:00
Ron Dreslinski
54ed57cc4c Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/tport.cc:
    Merge PacketPtr changes

--HG--
extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
2006-10-20 13:04:59 -04:00
Ron Dreslinski
28e9641c2c Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20 13:01:21 -04:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-20 00:10:12 -07:00
Nathan Binkert
7245d4530d refactor code for the packet, get rid of packet_impl.hh
and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19 23:38:45 -07:00
Ron Dreslinski
5bcdc74fe2 Fix WriteInvalidateResp
--HG--
extra : convert_revision : ac4281944202a9a2f166b305a1eaea507e484bcc
2006-10-18 16:38:02 -04:00
Ali Saidi
2c9d506f46 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

src/mem/packet.hh:
    hand merge

--HG--
extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
2006-10-12 14:18:42 -04:00
Ali Saidi
3ba2ed6aef add a traceflag for functional accesses
implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such

src/base/traceflags.py:
    add a traceflag for functional accesses
src/mem/packet.cc:
    implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
    add the ability to print a packet to an ostream
    remove tabs in file
    mark const functions as such

--HG--
extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
2006-10-12 14:15:09 -04:00
Ron Dreslinski
567afbf6ce More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
    Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Debug output.
    Clean up memleak in atomic mode.
    Set hitLatency.
    Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
    Add command strings for new commands
src/python/m5/objects/MemTest.py:
    Add param to test atomic memory.

--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11 18:28:33 -04:00
Gabe Black
404b2a951d Fixed a corner case and simplified the logic in Packet::intersect.
--HG--
extra : convert_revision : b57c31ca7c220e701d34e02bb07ce392370e4428
2006-10-10 17:49:31 -04:00
Ron Dreslinski
fc281d0b64 Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on

src/SConscript:
    Add in compilation flags for cache files
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
    Back in more fixes, now base_cache compiles
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lru.cc:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/request.hh:
    Backing in more changsets, getting closer to compile

--HG--
extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
2006-06-28 14:35:00 -04:00