Commit graph

11340 commits

Author SHA1 Message Date
Andreas Sandberg
5a249e03a4 stats: Update to reflect changes to RealView platform code 2015-12-04 00:19:05 +00:00
Andreas Sandberg
6a05179e13 arm, config: Automatically discover available platforms
Add support for automatically discover available platforms. The
Python-side uses functionality similar to what we use when
auto-detecting available CPU models. The machine IDs have been updated
to match the platform configurations. If there isn't a matching
machine ID, the configuration scripts default to -1 which Linux uses
for device tree only platforms.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
b3f7a62876 dev, arm: Disable R/B swap in HDLCD by default
The HDLCD model implements a workaround that swaps the red and blue
channels. This works around an issue in certain old kernels. The new
driver doesn't seem to have this behavior, so disable the workaround
by default and enable it in the affected platforms.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
4aeaaf7985 dev, arm: Split MCC and DCC subsystems
Devices behind the Versatile Express configuration controllers are
currently all lumped into one SimObject. This will make DTB generation
challenging since the DTB assumes them to be in different parts of the
hierarchy. It also makes it hard to model other CoreTiles without also
replicating devices from the motherboard.

This changeset splits the VExpressCoreTileCtrl into two subsystems:
VExpressMCC for all motherboard-related devices and CoreTile2A15DCC
for Core Tile specific devices.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
daa53da594 sim: Add support for generating back traces on errors
Add functionality to generate a back trace if gem5 crashes (SIGABRT or
SIGSEGV). The current implementation uses glibc's stack traversal
support if available and stubs out the call to print_backtrace()
otherwise.
2015-12-04 00:12:58 +00:00
Andreas Sandberg
a1aeff27ce arm: Add support for automatic boot loader selection
Add support for automatically selecting a boot loader that matches the
guest system's kernel. Instead of accepting a single boot loader, the
ArmSystem class now accepts a vector of boot loaders. When
initializing a system, the we now look for the first boot loader with
an architecture that matches the kernel.

This changeset makes it possible to use the same system for both
64-bit and 32-bit kernels.
2015-12-03 23:53:37 +00:00
Andreas Sandberg
146dfd0356 dev, mips: Remove the unused MaltaPChip class
The MaltaPChip class is currently unused and identical (except for the
class name) to the TsunamiPChip. If someone decides to implement PCI
for Malta, they should make sure to share code with the Tsunami
implementation if they are similar.
2015-12-03 23:09:34 +00:00
Andreas Hansson
00b2bd7437 stats: Bump stats to match current behaviour 2015-12-02 09:58:24 -05:00
Andreas Sandberg
c84745e2cb config: Fix broken SimObject listing
The gem5 option '--list-sim-objects' is supposed to list all available
SimObjects and their parameters. It currently chokes on SimObjects
with parameters that have an object instance as their default
value. This is caused by __str__ in SimObject trying to resolve its
complete path. When the path resolution method reaches the parent
object (a MetaSimObject since it hasn't been instantiated), it dies
with a Python exception.

This changeset adds a guard to stop path resolution if the parent
object is a MetaSimObject.
2015-12-01 13:01:05 +00:00
Andreas Sandberg
d7e3d94c14 dev: Remove unnecessary header include
--HG--
extra : rebase_source : 64046371962e98413757bc3ab0c0d48dfb11ff1e
2015-11-24 10:13:04 +00:00
Andreas Hansson
72b14f7ef6 mem: Fix search-replace issues in DRAMPower wrapper license
Fix a number of unintentional insertions of 'const'.
2015-11-25 13:52:56 -05:00
Andrew Bardsley
4375678a0d config: Added missing types to JSON/INI Python reader
Added the missing types EthernetAddr and Current to the JSON/INI file
reader example configs/example/read_config.py.

Also added __str__ to EthernetAddr to make values appear in the same form
in JSON an INI files.
2015-11-22 05:10:21 -05:00
Andrew Bardsley
4596a33e10 sim: Update C++ config example to match SystemC example
Update the use of the drain manager, and checkpointing to
match changes to gem5 since the example was written.
2015-09-10 16:10:49 +01:00
Geoffrey Blake
1e1cd2dc01 arm, dev: Fix flash model serialization code typos
The flash model has typos in its serialization code for
unknownPages, locationTable, blockValidEntries, and blockEmptyEntries
arrays where it would save each entry in the array under the same
name in the checkpoint.  This patch fixes these typos.
2015-11-22 05:10:19 -05:00
Nathanael Premillieu
488128dab2 cpu: Fix base FP and CC register index in o3 insertThread()
Note that the method is not used, and could possibly be deleted.
2015-11-22 05:10:19 -05:00
Nathanael Premillieu
bbdd7cecb9 arm: Fix fplib 128-bit shift operators
Appease clang.
2015-11-22 05:10:18 -05:00
Andreas Hansson
6adb728fb4 config: Minor fixes to the DRAM utilisation sweep 2015-11-22 05:10:17 -05:00
Andreas Hansson
949437d559 cpu: Fix memory leak in traffic generator
In cases where we discard the packet, make sure to also delete it and
the associated request.
2015-11-22 05:10:16 -05:00
Andreas Sandberg
d57a855e40 cpu: Enforce 1 interrupt controller per thread
Consider it a fatal configuration error if the number of interrupt
controllers doesn't match the number of threads in an SMT
configuration.
2015-11-20 14:50:17 -06:00
Nilay Vaish
90d430d5b3 Merged changesets: 47e2adf7fb1a and b65d4e878ed2
--HG--
extra : amend_source : c51de9ae5387aba6fae8403677054678beceb2ab
2015-11-16 05:10:45 -06:00
Nilay Vaish
de489e1997 stats: updates due to recent chagnesets 2015-11-16 05:08:57 -06:00
Swapnil Haria
08cec03f8e x86: Invalidating TLB entry on page fault
As per the x86 architecture specification, matching TLB entries need to be
invalidated on a page fault. For instance, after a page fault due to inadequate
protection bits on a TLB hit, the TLB entry needs to be invalidated. This
behavior is clearly specified in the x86 architecture manuals from both AMD and
Intel.  This invalidation is missing currently in gem5, due to which linux
kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
removes a tlb flush on updating page table entries in x86.

Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
due to repeated page faults (~300000 before the first print statement in a
bash file). Ensured that page fault rate drops drastically and observed
reduction in boot time from order of hours to minutes for linux kernel v3.8
and v3.11
2015-11-16 05:08:54 -06:00
Bjoern A. Zeeb
f50e92d2c7 x86: cpuid: add family to warn() message
doCpuid() has to identical warn messages about unimplemented functions.  Add
the family to the log message to make them distinguishable.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16 04:58:39 -06:00
Bjoern A. Zeeb
5c49635f20 x86: pagetable walker: fix typo in comment 2015-11-16 04:58:39 -06:00
Palle Lyckegaard
a95e8ab887 sparc: Make remote debugging with gdb work
Remove sparc V8 TBR register from list of registers since it is not part of
sparc V9. This brings the number of registers in sync with what gdb expects

Without this patch gdb complains about receoved packet too long.

with this patch gdb is able to work properly with gem5 for remote debugging.

Note: gdb is version 7.8
Note: gdb is configured with --target=sparc64-sun-solaris2.8

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16 04:58:39 -06:00
Nilay Vaish
e1385784f2 stats: remove wb_penalized and wb_penalized_rate 2015-11-16 04:58:29 -06:00
Nilay Vaish
1d268a1f2d o3: drop unused statistic wbPenalized and wbPenalizedRate 2015-11-16 04:57:52 -06:00
Joe Gross
fe9cf5100a sim: support for distcc pump server settings 2015-11-15 17:56:43 -05:00
Andreas Sandberg
2a6fe97092 arm: Add missing explicit overrides for classic caches
Make clang when compiling on OSX.
2015-11-15 21:28:00 +00:00
Brad Beckmann
95f20a2905 ruby: added stl vector of ints to be used by SLICC 2015-07-20 09:15:20 -05:00
Tony Gutierrez
d10fac27bc slicc: fixes for the Address to Addr changeset (11025)
misc changes now that Address has become Addr including int to address util
function
2015-11-13 17:30:58 -05:00
Joe Gross
5143d480f3 ruby: add BoolVec
The BoolVec typedef and insertion operator overload function simplify usage of
vectors of type bool
2015-11-13 17:30:56 -05:00
Brad Beckmann
aef8d851bd mem: add boolean to disable PacketQueue's size sanity check
the sanity check, while generally useful for exposing memory system bugs,
may be spurious with respect to GPU workloads, which may generate many more
requests than typical CPU workloads. the large number of requests generated
by the GPU may cause the req/resp queues to back up, thus queueing more than
100 packets.
2015-07-20 09:15:18 -05:00
Anthony Gutierrez
7678ddeb46 misc: ignore object files and static libs in util/m5 2015-11-13 17:03:48 -05:00
Andreas Sandberg
0ee18f5b66 dev, arm: Initialized the iccrpr register in the GIC
The IICRPR register in the GIC is currently not being initialized when
the GIC is instantiated. Initialize to the value mandated by the
architecture specification.
2015-11-11 10:18:38 +00:00
Sascha Bischoff
9d23e6d323 dev: Add basic checkpoint support to VirtIO9PProxy device
This patch adds very basic checkpoint support for the VirtIO9PProxy
device. Previously, attempts to checkpoint gem5 with a present 9P
device caused gem5 to fatal as none of the state is tracked. We still
do not track any state, but we replace the fatal with a warning which
is triggered if the device has been used by the guest system. In the
event that it has not been used, we assume that no state is lost
during checkpointing. The warning is triggered on both a serialize and
an unserialize to ensure maximum visibility for the user.
2015-11-05 09:40:12 +00:00
Andreas Sandberg
9719b261a1 dev: Remove unused header includes
Devices should never need to include dev/pciconfall.hh.

--HG--
extra : amend_source : 3a6e56485d432b49e2af22407982fa785c0ccb68
2015-11-09 13:44:15 +00:00
Andreas Sandberg
c62fe43ba9 dev: Don't access the platform directly in PCI devices
Cleanup PCI devices to avoid using the PciDevice::platform pointer
directly. The PCI-specific functionality provided by the Platform
should be accessed through the wrappers in PciDevice.
2015-11-09 13:44:04 +00:00
Andreas Hansson
324bc9771d stats: Update stats to match cache changes 2015-11-06 03:26:50 -05:00
Andreas Hansson
337774e192 config: Update memtest to stress test clean writebacks
This patch adds yet another twist to the memtest cache hierarchy, in that
the writeback_clean option is toggled at every level to match the
clusivity of the downstream cache.
2015-11-06 03:26:44 -05:00
Andreas Hansson
7433d77fcf mem: Add an option to perform clean writebacks from caches
This patch adds the necessary commands and cache functionality to
allow clean writebacks. This functionality is crucial, especially when
having exclusive (victim) caches. For example, if read-only L1
instruction caches are not sending clean writebacks, there will never
be any spills from the L1 to the L2. At the moment the cache model
defaults to not sending clean writebacks, and this should possibly be
re-evaluated.

The implementation of clean writebacks relies on a new packet command
WritebackClean, which acts much like a Writeback (renamed
WritebackDirty), and also much like a CleanEvict. On eviction of a
clean block the cache either sends a clean evict, or a clean
writeback, and if any copies are still cached upstream the clean
evict/writeback is dropped. Similarly, if a clean evict/writeback
reaches a cache where there are outstanding MSHRs for the block, the
packet is dropped. In the typical case though, the clean writeback
allocates a block in the downstream cache, and marks it writable if
the evicted block was writable.

The patch changes the O3_ARM_v7a L1 cache configuration and the
default L1 caches in config/common/Caches.py
2015-11-06 03:26:43 -05:00
Andreas Hansson
afa252b0b9 config: Update memtest to stress test cache clusivity
This patch adds an new twist to the memtest cache hierarchy, in that
it switches from mostly inclusive to mostly exclusive at every level
in the tree. This has helped weed out plenty issues, and serves as a
good stress tests.
2015-11-06 03:26:42 -05:00
Andreas Hansson
654266f39c mem: Add cache clusivity
This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.

The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.

This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.

Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.

The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
2015-11-06 03:26:41 -05:00
Ali Jafri
f02a9338c1 mem: Avoid unnecessary snoops on writebacks and clean evictions
This patch optimises the handling of writebacks and clean evictions
when using a snoop filter. Instead of snooping into the caches to
determine if the block is cached or not, simply set the status based
on the snoop-filter result.
2015-11-06 03:26:40 -05:00
Andreas Hansson
c086c20bd2 mem: Order packet queue only on matching addresses
Instead of conservatively enforcing order for all packets, which may
negatively impact the simulated-system performance, this patch updates
the packet queue such that it only applies the restriction if there
are already packets with the same address in the queue.

The basic need for the order enforcement is due to coherency
interactions where requests/responses to the same cache line must not
over-take each other. We rely on the fact that any packet that needs
order enforcement will have a block-aligned address. Thus, there is no
need for the queue to know about the cacheline size.
2015-11-06 03:26:38 -05:00
Ali Jafri
52c8ae5187 mem: Enforce insertion order on the cache response path
This patch enforces insertion order transmission of packets on the
response path in the cache. Note that the logic to enforce order is
already present in the packet queue, this patch simply turns it on for
queues in the response path.

Without this patch, there are corner cases where a request-response is
faster than a response-response forwarded through the cache. This
violation of queuing order causes problems in the snoop filter leaving
it with inaccurate information. This causes assert failures in the
snoop filter later on.

A follow on patch relaxes the order enforcement in the packet queue to
limit the performance impact.
2015-11-06 03:26:37 -05:00
Andreas Hansson
6b70afd0d4 mem: Use the packet delays and do not just zero them out
This patch updates the I/O devices, bridge and simple memory to take
the packet header and payload delay into account in their latency
calculations. In all cases we add the header delay, i.e. the
accumulated pipeline delay of any crossbars, and the payload delay
needed for deserialisation of any payload.

Due to the additional unknown latency contribution, the packet queue
of the simple memory is changed to use insertion sorting based on the
time stamp. Moreover, since the memory hands out exclusive (non
shared) responses, we also need to ensure ordering for reads to the
same address.
2015-11-06 03:26:36 -05:00
Andreas Hansson
8bc925e36d mem: Align rules for sinking inhibited packets at the slave
This patch aligns how the memory-system slaves, i.e. the various
memory controllers and the bridge, identify and deal with sinking of
inhibited packets that are only useful within the coherent part of the
memory system.

In the future we could shift the onus to the crossbar, and add a
parameter "is_point_of_coherence" that would allow it to sink the
aforementioned packets.
2015-11-06 03:26:35 -05:00
Andreas Hansson
8e55d51aaa mem: Do not treat CleanEvict as a write operation
This patch changes the CleanEvict command type to not be considered a
write. Initially it was made a zero-sized write to match the writeback
command, but as things developed it became clear that it causes more
problems than it solves. For example, the memory modules (and bridge)
should not consider the CleanEvict as a write, but instead discard
it. With this patch it will be neither a read, nor write, and as it
does not need a response the slave will simply sink it.
2015-11-06 03:26:33 -05:00
Andreas Hansson
ac1368df50 mem: Unify delayed packet deletion
This patch unifies how we deal with delayed packet deletion, where the
receiving slave is responsible for deleting the packet, but the
sending agent (e.g. a cache) is still relying on the pointer until the
call to sendTimingReq completes. Previously we used a mix of a
deletion vector and a construct using unique_ptr. With this patch we
ensure all slaves use the latter approach.
2015-11-06 03:26:21 -05:00