src/cpu/simple/timing.cc:
Record numCycles stat properly.
src/cpu/simple/timing.hh:
Extra variable to help record numCycles stat.
--HG--
extra : convert_revision : 343311902831820264878aad41dc619999726b6b
src/cpu/o3/commit_impl.hh:
Fixes for compile and sampling.
src/cpu/o3/cpu.cc:
Deallocate and activate threads properly. Also hopefully fix being able to use caches while switching over.
src/cpu/o3/cpu.hh:
Fixes for deallocating and activating threads.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit.hh:
Handle getting back a BadAddress result from the access.
src/cpu/o3/iew_impl.hh:
More debug output.
src/cpu/o3/lsq_unit_impl.hh:
Fixup store conditional handling (still a bit of a hack, but works now).
Also handle getting back a BadAddress result from the access.
src/cpu/o3/thread_context_impl.hh:
Deallocate context now records if the context should be fully removed.
--HG--
extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9
src/SConscript:
Include MemTest for now. It's not complete but it compiles so it shouldn't mess anything else up.
--HG--
extra : convert_revision : 15a610c855b677fdced817850c92e4c911cf6d1c
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.
src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
add the periodicity of checkpointing back into the code.
to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.
--HG--
extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
src/arch/alpha/isa_traits.hh:
This got changed to the wrong version by accident.
src/cpu/base.cc:
Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
Switch out updates from the version of m5 I have. Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
Use proper method to get flags. Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
Support profiling.
src/cpu/ozone/cpu.hh:
Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
Get flags correctly.
src/cpu/ozone/thread_state.hh:
Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext.
--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
src/cpu/o3/fetch_impl.hh:
Fix ordering so dereference works
src/cpu/o3/lsq_impl.hh:
Check to make sure we didn't squash already
src/cpu/o3/lsq_unit.hh:
Fix for counting squashed retrys in the WB count
src/cpu/o3/lsq_unit_impl.hh:
Make sure to set retryID for stores, and clear it appropriately
--HG--
extra : convert_revision : 689765a1baea7b36f13eb177d65e97b52b6da09f
src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
Options to turn on output after every instruction. They are commented out.
--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
src/arch/mips/isa/base.isa:
special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
change comment
--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!
Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )
src/arch/alpha/isa/mem.isa:
spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
Gabe really authored this
src/arch/mips/isa/decoder.isa:
add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
Steven really did this file
src/arch/mips/isa/formats/branch.isa:
fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
update LoadStoreBase template
src/arch/mips/isa_traits.cc:
update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
add in nextNPC variable and supporting functions.
add isCondDelaySlot function
Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
init nextNPC
src/cpu/o3/SConscript:
add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
add some extra communication variables to aid in handling the
delay slots
src/cpu/o3/commit.hh:
minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
Update function interface ...
adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
update removeInstsNotInROB
src/cpu/o3/decode.hh:
declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
no need for my name here
src/cpu/o3/isa_specific.hh:
add in MIPS files
src/cpu/o3/scoreboard.hh:
dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
MIPS file for O3CPU...mirrors ALPHA definition
--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/fs.py:
Hand merge.
--HG--
extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
SConstruct:
Include an option to specify the CPUs being tested.
src/cpu/SConscript:
Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker.
src/python/m5/objects/O3CPU.py:
Include default options. Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used.
tests/SConscript:
Several minor updates (sorry for one commit). Updated the copyright and fixed some m5 style issues. Also added the ability to specify which CPUs to run the tests on.
--HG--
extra : convert_revision : b0b801115705544ea02e572e31314f7bb8b5f0f2
Add a max time option in seconds and a single system root clock be 1THz
configs/test/fs.py:
Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Enforce the timing cpu ticking at it's clock rate
--HG--
extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
src/cpu/checker/cpu.hh:
Don't count checker's instructions towards total instructions committed.
src/python/m5/objects/Root.py:
Set default clock to 1 THz.
--HG--
extra : convert_revision : 0b5eaa197c860c361a3b00087e45ddc249ff1918
Right now only non-SMT SE regression tests have been added back in. The rest are pending getting SMT working, and consolidating the FS configuration files.
Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.
Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work. The test itself should probably work once the code is fixed.
SConstruct:
Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.
--HG--
extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2
src/cpu/o3/lsq_unit.hh:
LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
LSQ needs to decrement the WB counter if the load is squashed.
--HG--
extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
src/arch/SConscript:
Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified.
src/cpu/SConscript:
Copy the CPU_MODELS from the env, don't create a proxy to it.
--HG--
extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
suspend context will now take the thread off the activeThread list.
src/arch/mips/isa_traits.cc:
add in copy MiscRegs unimplemented function
--HG--
extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
src/cpu/o3/lsq.hh:
Update to have LSQ work with only one dcache port for all LSQ Units. LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Update for LSQ to create dcache port instead of LSQUnits. Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.
--HG--
extra : convert_revision : 2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
Since se mode has a system, allow access to it
Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
Since se mode has a system, allow access to it
Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
Implement drain() support in devices
src/python/m5/config.py:
Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
memory mode information now contained in system object
--HG--
extra : convert_revision : 1389c77e66ee6d9710bf77b4306fb47e107b21cf
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/test.py:
Hand merge.
--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
src/cpu/o3/commit_impl.hh:
Always set instruction. This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
Change serialization so it matches other CPU's output. Also fix up some indexing.
--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
src/cpu/o3/fetch_impl.hh:
Hand merge.
--HG--
extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).
src/cpu/o3/fetch_impl.hh:
Fix ordering issue with squashed Icache Fetches and Static data in packet.
--HG--
extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
