Commit graph

10472 commits

Author SHA1 Message Date
Andreas Hansson
acdfcad30d base: Use shared_ptr for stat Node
This patch transitions the stat Node and its derived classes from
the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no
changes in behaviour, and the code modifications are mainly replacing
"new" with "make_shared".
2014-10-16 05:49:48 -04:00
Andreas Hansson
8b789ae451 base: Transition CP annotate to use shared_ptr 2014-10-16 05:49:47 -04:00
Andreas Hansson
ad3f75dc81 dev: Use shared_ptr for EthPacketData
This patch transitions the EthPacketData from the ad-hoc
RefCountingPtr to the c++11 shared_ptr. There are no changes in
behaviour, and the code modifications are mainly replacing "new" with
"make_shared".

The bool casting operator for the shared_ptr is explicit, and we must
therefore either cast it, compare it to NULL (p != nullptr), double
negate it (!!p) or do a (p ? true : false).
2014-10-16 05:49:46 -04:00
Andreas Hansson
4e67ab6663 dev: Use shared_ptr for Arguments::Data
This patch takes a first few steps in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr. There are no changes in
behaviour, and the code modifications are mainly introducing the
use of make_shared.

Note that the class could use unique_ptr rather than shared_ptr, was
it not for the postfix increment and decrement operators.
2014-10-16 05:49:45 -04:00
Andreas Hansson
2475862747 arch,x86,mem: Dynamically determine the ISA for Ruby store check
This patch makes the memory system ISA-agnostic by enabling the Ruby
Sequencer to dynamically determine if it has to do a store check. To
enable this check, the ISA is encoded as an enum, and the system
is able to provide the ISA to the Sequencer at run time.

--HG--
rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
2014-10-16 05:49:44 -04:00
Andreas Hansson
df973abef3 mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.
2014-10-16 05:49:43 -04:00
Andreas Sandberg
37908d62a4 arm: Add helper methods to setup architected PMU events 2014-10-16 05:49:42 -04:00
Andreas Sandberg
e0074324ba cpu: Probe points for basic PMU stats
This changeset adds probe points that can be used to implement PMU
counters for CPU stats. The following probes are supported:

  * BaseCPU::ppCycles / Cycles
  * BaseCPU::ppRetiredInsts / RetiredInsts
  * BaseCPU::ppRetiredLoads / RetiredLoads
  * BaseCPU::ppRetiredStores / RetiredStores
  * BaseCPU::ppRetiredBranches RetiredBranches
2014-10-16 05:49:41 -04:00
Andreas Sandberg
9d35d48e84 arm: Add TLB PMU probes
This changeset adds probe points that can be used to implement PMU
counters for TLB stats. The following probes are supported:

* ArmISA::TLB::ppRefills / TLB Refills (TLB insertions)
2014-10-16 05:49:41 -04:00
Andreas Sandberg
76b0ff9ecd cpu: Add branch predictor PMU probe points
This changeset adds probe points that can be used to implement PMU
counters for branch predictor stats. The following probes are
supported:

 * BPRedUnit::ppBranches / Branches
 * BPRedUnit::ppMisses / Misses
2014-10-16 05:49:40 -04:00
Andreas Sandberg
3697990c27 arm: Add a model of an ARM PMUv3
This class implements a subset of the ARM PMU v3 specification as
described in the ARMv8 reference manual. It supports most of the
features of the PMU, however the following features are known to be
missing:

 * Event filtering (e.g., from different privilege levels).
 * Access controls (the PMU currently ignores the execution level).
 * The chain counter (event no. 0x1E) is unimplemented.

The PMU itself does not implement any events, it merely provides an
interface for the configuration scripts to hook up probes that drive
events. Configuration scripts should call addEventProbe() to configure
custom events or high-level methods to configure architected
events. The Python implementation of addEventProbe() automatically
delays event type registration until after instantiation.

In order to support CPU switching and some combined counters (e.g.,
memory references synthesized from loads and stores), the PMU allows
multiple probes per event type. When creating a system that switches
between CPU models that share the same PMU, PMU events for all of the
CPU models can be registered with the PMU.

Kudos to Matt Horsnell for the initial gem5 implementation of the PMU.
2014-10-16 05:49:39 -04:00
Andreas Sandberg
132ea6319a sim: Add typedefs for PMU probe points
In order to show make PMU probe points usable across different PMU
implementations, we want a common probe interface. This patch the
namespace ProbePoins that contains typedefs for probe points that are
shared between multiple SimObjects. It also adds typedefs for the PMU
probe interface.
2014-10-16 05:49:38 -04:00
Andreas Sandberg
804ed4b418 sim: Add support for serializing BitUnionXX
BitUnion instances can normally not be used with the SERIALIZE_SCALAR
and UNSERIALIZE_SCALAR macros due to the way they are converted
between their storage type and their actual type. This changeset adds
a set of parm(In|Out) functions specifically for gem5 bit unions to
work around the issue.
2014-10-16 05:49:37 -04:00
Andreas Hansson
66df7b7fd4 config: Add the ability to read a config file using C++ and Python
This patch adds the ability to load in config.ini files generated from
gem5 into another instance of gem5 built without Python configuration
support. The intended use case is for configuring gem5 when it is a
library embedded in another simulation system.

A parallel config file reader is also provided purely in Python to
demonstrate the approach taken and to provided similar functionality
for as-yet-unknown use models. The Python configuration file reader
can read both .ini and .json files.

C++ configuration file reading:

A command line option has been added for scons to enable C++ configuration
file reading: --with-cxx-config

There is an example in util/cxx_config that shows C++ configuration in action.
util/cxx_config/README explains how to build the example.

Configuration is achieved by the object CxxConfigManager. It handles
reading object descriptions from a CxxConfigFileBase object which
wraps a config file reader. The wrapper class CxxIniFile is provided
which wraps an IniFile for reading .ini files. Reading .json files
from C++ would be possible with a similar wrapper and a JSON parser.

After reading object descriptions, CxxConfigManager creates
SimObjectParam-derived objects from the classes in the (generated with this
patch) directory build/ARCH/cxx_config

CxxConfigManager can then build SimObjects from those SimObjectParams (in an
order dictated by the SimObject-value parameters on other objects) and bind
ports of the produced SimObjects.

A minimal set of instantiate-replacing member functions are provided by
CxxConfigManager and few of the member functions of SimObject (such as drain)
are extended onto CxxConfigManager.

Python configuration file reading (configs/example/read_config.py):

A Python version of the reader is also supplied with a similar interface to
CxxConfigFileBase (In Python: ConfigFile) to config file readers.

The Python config file reading will handle both .ini and .json files.

The object construction strategy is slightly different in Python from the C++
reader as you need to avoid objects prematurely becoming the children of other
objects when setting parameters.

Port binding also needs to be strictly in the same port-index order as the
original instantiation.
2014-10-16 05:49:37 -04:00
Andreas Hansson
b14f521e5f scons: Add Undefined Behavior Sanitizer (UBSan) option
This patch adds the Undefined Behavior Sanitizer (UBSan) for clang and
gcc >= 4.9. Due to the performance impact, the usage is guarded by a
command-line option.
2014-10-16 05:49:36 -04:00
Curtis Dunham
ded540a661 scons: Add --without-tcmalloc build option
Disabling tcmalloc is required for valgrind's memcheck to work properly;
this option makes it easier to create such a build.
2014-09-22 14:37:23 -05:00
Curtis Dunham
f7c6a2cbed scons: Generate a single debug flag C++ file
Reduces target count/compiler invocations by ~180.
2014-08-12 17:35:28 -05:00
Curtis Dunham
f780e85dc3 scons: create dummy target to have SWIG generate C++ classes
scons build/<arch>/swig
2014-10-16 05:49:33 -04:00
Andrew Bardsley
d8502ee46d config: Add a --without-python option to build process
Add the ability to build libgem5 without embedded Python or the
ability to configure with Python.

This is a prelude to a patch to allow config.ini files to be loaded
into libgem5 using only C++ which would make embedding gem5 within
other simulation systems easier.

This adds a few registration interfaces to things which cross
between Python and C++.  Namely: stats dumping and SimObject resolving
2014-10-16 05:49:32 -04:00
Andreas Hansson
a63ba6c7b7 stats: Small bump of trailing stats
Somehow these seem to have been missed.
2014-10-16 05:49:31 -04:00
Nilay Vaish
1efe42fa97 stats: updates due to changes to x86, stale configs. 2014-10-11 16:18:51 -05:00
Andrew Lukefahr
8e07b36d2b cpu: Fix o3 SMT IQCount bug
Commmitted by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-11 16:16:02 -05:00
Nilay Vaish
19ca35737d util: adds a script for using DSENT
This patch adds a python script that processes the configuration and the
statistics file from a simulation run.  Configuration and activity of network
routers and links obtained from this processing is fed to DSENT via its Python
interface.  DSENT then computes the area and the power consumption of these
network components.  The script outputs these quantities to the console.
2014-10-11 16:16:00 -05:00
Nilay Vaish
c1aecc05e6 ext: dsent: adds a Python interface, drops C++ one
This patch extensively modifies DSENT so that it can be accessed using Python.
To access the Python interface, DSENT needs to compiled as a shared library.
For this purpose a CMakeLists.txt file has been added.  Some of the code that
is not required is being removed.
2014-10-11 16:16:00 -05:00
Nilay Vaish
e8ed7b1d1b ext: add the source code for DSENT
This patch adds a tool called DSENT to the ext/ directory.  DSENT
is a tool that models power and area for on-chip networks.  The next
patch adds a script for using the tool.
2014-10-11 15:02:23 -05:00
Nilay Vaish
a098fad174 ruby: network: garnet: add statistics for different activities
This patch adds some statistics to garnet that record the activity
of certain structures in the on-chip network.  These statistics, in a later
patch, will be used for computing the energy consumed by the on-chip network.
2014-10-11 15:02:23 -05:00
Nilay Vaish
25bb18f12b ruby: network: garnet: remove functions for computing power 2014-10-11 15:02:23 -05:00
Nilay Vaish
9321a41c62 ruby: drop Orion network power model
Orion is being dropped from ruby.  It would be replaced with DSENT
which has better models.  Note that the power / energy numbers reported
after this patch has been applied are not for use.
2014-10-11 15:02:23 -05:00
Nilay Vaish
b6d804a1e6 ruby: mesi: slight renaming 2014-10-11 15:02:23 -05:00
Nilay Vaish
b80e574d01 config: separate function for instantiating a memory controller
This patch moves code for instantiating a single memory controller from
the function config_mem() to a separate function.  This is being done
so that memory controllers can be instantiated without assuming that
they will be attached to the system in a particular fashion.
2014-10-11 15:02:23 -05:00
Nilay Vaish
e7f918d8cd ruby: structures: coorect #ifndef macros in header files 2014-10-11 15:02:22 -05:00
Nilay Vaish
0f28d63272 ruby: moesi hammer: correct typo in master-slave assignment 2014-10-11 15:02:22 -05:00
Jiuyue Ma
9fb8b8515b x86: add LongModeAddressSize function to cpuid
LongModeAddressSize was used by kernel 2.6.28.4 for physical address
validation, if not properly implemented, PCI resource allocation may
failed because of ioremap failed:

- linux-2.6.28.4/arch/x86/mm/ioremap.c:27-30
  27 static inline int phys_addr_valid(unsigned long addr)
  28 {
  29     return addr < (1UL << boot_cpu_data.x86_phys_bits);
  30 }

- linux-2.6.28.4/arch/x86/kernel/cpu/common.c:475-482
 475 #ifdef CONFIG_X86_64
 476         if (c->extended_cpuid_level >= 0x80000008) {
 477                 u32 eax = cpuid_eax(0x80000008);
 478
 479                 c->x86_virt_bits = (eax >> 8) & 0xff;
 480                 c->x86_phys_bits = eax & 0xff;
 481         }
 482 #endif

- linux-2.6.28.4/arch/x86/mm/ioremap.c:209-214
 209 if (!phys_addr_valid(phys_addr)) {
 210     printk(KERN_WARNING "ioremap: invalid physical address %llx\n",
 211            (unsigned long long)phys_addr);
 212     WARN_ON_ONCE(1);
 213     return NULL;
 214 }

This patch return 0x0000ffff for LongModeAddressSize, which guarantee phys_addr_valid never failed.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-06-13 16:48:47 +08:00
Jiuyue Ma
e1a5522a89 config, x86: Ensure that PCI devs get bridged to the memory bus
This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by
reserve anything between the end of memory and 3GB if memory is less
than 3GB. It also statically bridge these address range to the IO bus,
which guaranty access to pci address space will pass though bridge to
iobus.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-07-17 12:05:41 +08:00
Jiuyue Ma
7d03bf4d6b config, x86: swap bus_id of ISA/PCI in X86 IntelMPTable
This patch assign bus_id=0 to PCI bus and bus_id=1 to ISA bus for
X86 platform. Because PCI device get config space address using
Pc::calcPciConfigAddr() which requires "assert(bus==0)".
This fixes PCI interrupt routing and discovery on Linux.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-07-17 11:00:12 +08:00
Andrew Lukefahr
f94fd44991 sim: draining bug for fast-forwaring multiple cores
fix draining bug where multiple cores hit max_insts_any_thread simultaneously

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-11 15:02:22 -05:00
Nilay Vaish
2816521f0d base: addr range: slight change to validity check
The validity check is being changed from < to <= since the end of the range
is considered to be a part of it.
2014-10-11 15:02:22 -05:00
Nilay Vaish
a9bfea5a35 base: misc: Add missing header file. 2014-10-11 15:02:22 -05:00
Andreas Hansson
0746e92cd3 stats: Add DRAM power statistics to reference output 2014-10-09 17:52:13 -04:00
Omar Naji
cd8023a1ee mem: DRAMPower integration for on-line DRAM power stats
This patch takes the final step in integrating DRAMPower and adds the
appropriate calls in the DRAM controller to provide the command trace
and extract the power and energy stats. The debug printouts are still
left in place, but will eventually be removed.

At the moment the DRAM power calculation is always on when using the
DRAM controller model. The run-time impact of this addition is around
1.5% when looking at the total host seconds of the regressions. We
deem this a sensible trade-off to avoid the complication of adding an
enable/disable mechanism.
2014-07-29 17:22:44 +01:00
Omar Naji
afc6ce6228 mem: Add DRAMPower wrapping class
This patch adds a class to wrap DRAMPower Library in gem5.
This class initiates an object of class MemorySpecification
of the DRAMPower Library, passes the parameters from DRAMCtrl.py
to this object and creates an object of drampower library using
the memory specification.
2014-07-29 17:29:36 +01:00
Omar Naji
00b37ffe50 mem: Add missig timing and current parameters to DRAM configs
This patch adds missing timing and current parameters to the existing
DRAM configs. These missing timing and current parameters are required
by DRAMPower for the DRAM power calculations. The missing values are
datasheet values of the specified DRAMs, and the appropriate
references are added for the variuos configs.
2014-07-25 10:05:59 +01:00
Omar Naji
f9fce9ba07 mem: Remove DRAMSim2 DDR3 configuration
This patch prunes the DDR3 config that was initially created to match
the default config of DRAMSim2. The config is not complete as it is,
and to avoid having to maintain it, the easiest way forward is to
simply prune it. Going forward we are adding power number etc to the
other configurations.
2014-10-09 17:52:04 -04:00
Andreas Hansson
e0e8b08a42 ext: Add DRAMPower to enable on-line DRAM power modelling
This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit
8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the
simulator. We have chosen this specific version of DRAMPower as it
provides the necessary functionality, and future updates will be
coordinated with the DRAMPower development team. The files added only
include the bits needed to build the library, thus excluding all
memory specifications, traces, and the stand-alone DRAMPower
command-line tool.

A future patch includes the DRAMPower functionality in the DRAM
controller, to enable on-line DRAM power modelling, and avoid using
post-processing of traces.
2014-10-09 17:52:03 -04:00
Andreas Hansson
c81517c293 config: Add Current as a parameter type
This patch adds the Python parameter type Current, which is used for
the DRAM power modelling (to start with). With this addition we avoid
implicit unit assumptions.
2014-10-09 17:52:00 -04:00
Mitch Hayenga
06f4b521aa cpu: Remove Ozone CPU from the source tree
The Ozone CPU is now very much out of date and completely
non-functional, with no one actively working on restoring it. It is a
source of confusion for new users who attempt to use it before
realizing its current state. RIP
2014-10-09 17:51:58 -04:00
Andreas Hansson
3f6dc3c571 scons: Warn for known gcc and swig incompatibilities 2014-10-09 17:51:57 -04:00
Andreas Hansson
f4a538f862 mem: Add packet sanity checks to cache and MSHRs
This patch adds a number of asserts to the cache, checking basic
assumptions about packets being requests or responses.
2014-10-09 17:51:56 -04:00
Andreas Hansson
4a453e8c95 mem: Allow packet queue to move next send event forward
This patch changes the packet queue such that when scheduling a send,
the queue is allowed to move the event forward.
2014-10-09 17:51:52 -04:00
Andreas Hansson
6498ccddb2 misc: Fix issues identified by static analysis
Another bunch of issues addressed.
2014-10-01 08:05:54 -04:00