5 commits

Author	SHA1	Message	Date
Nilay Vaish	99fb8f8140	stats: changes to due to recent set of patches	2015-03-09 09:39:09 -05:00
Andreas Hansson	8909843a76	stats: Update stats to reflect cache and interconnect changes ... This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.	2015-03-02 05:04:20 -05:00
Andreas Hansson	df8df4fd0a	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes ... Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.	2014-12-23 09:31:20 -05:00
Andreas Hansson	6489598fb4	stats: Bump stats for fixes, mostly TLB and WriteInvalidate	2014-12-02 06:08:25 -05:00
Ali Saidi	29cd50e14e	arm, tests: Add 64-bit ARM regression tests	2014-10-29 23:50:15 -05:00