Commit graph

6183 commits

Author SHA1 Message Date
Korey Sewell
98b1452058 inorder-miscregs: Fix indexing for misc. reg operands and update result-types for better tracing of these types of values 2009-05-12 15:01:14 -04:00
Korey Sewell
2012202b06 inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
2009-05-12 15:01:14 -04:00
Korey Sewell
b569f8f0ed inorder-bpred: edits to handle non-delay-slot ISAs
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
2009-05-12 15:01:14 -04:00
Korey Sewell
1c8dfd9254 inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
2009-05-12 15:01:13 -04:00
Korey Sewell
63db33c4b1 isa-parser: made a few changes, but not author-worthy 2009-05-12 15:01:13 -04:00
Korey Sewell
a63cc2ff5f Merge Ruby Stuff 2009-05-11 19:44:34 -04:00
Nathan Binkert
f21e80ec72 ruby: assert(false) should be panic.
This also fixes some compiler warnings
2009-05-11 16:32:32 -07:00
Nathan Binkert
c2c68c66b7 stats: remove a few compat leftovers 2009-05-11 11:18:09 -07:00
Nathan Binkert
20f1da8b96 python: pull out common code from main that processes arguments 2009-05-11 11:18:09 -07:00
Nathan Binkert
5de3b2b6f0 stats: forgot an include for the mysql stuff 2009-05-11 11:18:09 -07:00
Nathan Binkert
5b752c1e31 scons: add include guards to info.hh 2009-05-11 11:18:09 -07:00
Nathan Binkert
cf6b4ef734 ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false
2009-05-11 10:38:46 -07:00
Steve Reinhardt
b174ec065e ruby: Initial references for ruby regressions 2009-05-11 10:38:46 -07:00
Steve Reinhardt
6df61e1f24 ruby: Set up Ruby regression tests. 2009-05-11 10:38:46 -07:00
Daniel Sanchez
93f2f69657 ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5.  Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
  tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-11 10:38:46 -07:00
Steve Reinhardt
ebf2f5aadd ruby: Check stderr and not stdin before hanging on an assert. 2009-05-11 10:38:46 -07:00
Polina Dudnik
7769cc9092 ruby: decommission code
1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory
2009-05-11 10:38:46 -07:00
Derek Hower
0ccf8f35a5 ruby: removed dead functions from the sequencer 2009-05-11 10:38:46 -07:00
Polina Dudnik
29f82f265a ruby: Removed g_SIMULATING flag
1. removed checks from tester files
2. removed else clause in Sequencer and DirectoryMemory else clause is
needed by the tester, it is up to Derek to revive it elsewhere when he
gets to it

Also:
1. Changed m_entries in DirectoryMemory to a map
2. And replaced SIMICS_read_physical_memory with a call to now-dummy
Derek's-to-be readPhysMem function
2009-05-11 10:38:46 -07:00
Polina Dudnik
b271090923 ruby: Remove transactional access types (e.g. LD_XACT) from CacheRequestType
1. Modified enumeration
2. Also modified profiler
3. Remove transactions from Tester
4. Edited XACT_MEM out of Synthetic Driver
2009-05-11 10:38:46 -07:00
Polina Dudnik
9f34659c52 ruby: reordered Debug and RubyConfig::init to fix segfault
due to uninitialized output file pointer.
2009-05-11 10:38:46 -07:00
Dan Gibson
8cbf8df5b7 ruby: Disabled RubyEventQueue's deletion of its home-grown priority heap.
Temporarily to fix unusual memory problem.
2009-05-11 10:38:46 -07:00
Nathan Binkert
7311fd7182 ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use.  This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time.  The easiest thing wound up being
to write a parser for slicc that would tell me.  Incidentally this
means we now have a slicc grammar written in python.
2009-05-11 10:38:46 -07:00
Nathan Binkert
e40b8e34c8 ruby: clean up a few warnings 2009-05-11 10:38:45 -07:00
Dan Gibson
8b9f70b9e4 ruby: Fixed some unresolved references. 2009-05-11 10:38:45 -07:00
Nathan Binkert
24da30e317 ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths.  Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
2009-05-11 10:38:45 -07:00
Dan Gibson
d8c592a05d ruby: remove unnecessary code.
1) Removing files from the ruby build left some unresovled
symbols. Those have been fixed.

2) Most of the dependencies on Simics data types and the simics
interface files have been removed.

3) Almost all mention of opal is gone.

4) Huge chunks of LogTM are now gone.

5) Handling 1-4 left ~hundreds of unresolved references, which were
fixed, yielding a snowball effect (and the massive size of this
delta).
2009-05-11 10:38:45 -07:00
Derek Hower
6ceaffd724 ruby: Cleaned up sequencer. Removed LogTM specific code. 2009-05-11 10:38:45 -07:00
Derek Hower
3d2acc547c ruby: added Packet interface to makeRequest and isReady.
Also pushed Packet usage into the Sequencer
2009-05-11 10:38:45 -07:00
Nathan Binkert
e1915f16d1 ruby: fold the debugging options into Debug.cc 2009-05-11 10:38:45 -07:00
Derek Hower
6e8373fad6 ruby: Renamed Ruby's EventQueue to RubyEventQueue
--HG--
rename : src/mem/ruby/eventqueue/EventQueue.cc => src/mem/ruby/eventqueue/RubyEventQueue.cc
rename : src/mem/ruby/eventqueue/EventQueue.hh => src/mem/ruby/eventqueue/RubyEventQueue.hh
rename : src/mem/ruby/eventqueue/EventQueueNode.cc => src/mem/ruby/eventqueue/RubyEventQueueNode.cc
rename : src/mem/ruby/eventqueue/EventQueueNode.hh => src/mem/ruby/eventqueue/RubyEventQueueNode.hh
2009-05-11 10:38:45 -07:00
Daniel Sanchez
ab5e4a22b3 ruby: Removed System name clash by renaming ruby's System to RubySystem 2009-05-11 10:38:44 -07:00
Nathan Binkert
84a18e7fdc ruby: rename config.include to config.hh and clean up the macro stuff.
I did the macro cleanup because I was worried that the SCons scanner
would get confused.  This code will hopefully go away soon anyway.

--HG--
rename : src/mem/ruby/config/config.include => src/mem/ruby/config/config.hh
2009-05-11 10:38:44 -07:00
Nathan Binkert
b05da09cd6 ruby: strip out some unused defines 2009-05-11 10:38:44 -07:00
Nathan Binkert
2f30950143 ruby: Import ruby and slicc from GEMS
We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
2009-05-11 10:38:43 -07:00
Korey Sewell
eea2b02b04 branch merge 2009-05-05 03:01:57 -04:00
Korey Sewell
c70241810d cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-05-05 02:51:31 -04:00
Korey Sewell
db79945ad0 merge code 2009-05-05 02:44:21 -04:00
Korey Sewell
9f90291c54 cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-05-05 02:39:05 -04:00
Nathan Binkert
dc35d2f125 scons: re-work the *Source functions to take more information.
Start by turning all of the *Source functions into classes
so we can do more calculations and more easily collect the data we need.
Add parameters to the new classes for indicating what sorts of flags the
objects should be compiled with so we can allow certain files to be compiled
without Werror for example.
2009-05-04 16:58:24 -07:00
Gabe Black
7146eb79f1 X86: Precompute the default and alternate address and operand size and the stack size. 2009-04-26 16:49:24 -07:00
Gabe Black
b6bfe8af26 X86: Split out the internal memory space from the regular translate() and precompute mode. 2009-04-26 16:48:44 -07:00
Gabe Black
4ee34dfb4e X86: Centralize updates to the handy M5 reg. 2009-04-26 16:47:48 -07:00
Gabe Black
06b3e3c303 X86: Implement lowest priority interrupts more correctly.
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
2009-04-26 02:09:54 -07:00
Gabe Black
2f34a7eaeb X86: Tell the function that sends int messages who to send to instead of figuring it out itself. 2009-04-26 02:09:27 -07:00
Gabe Black
88ab4bb257 X86: Make the local APICs register themselves with the IO APIC.
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
2009-04-26 02:09:13 -07:00
Gabe Black
c5e2cf841d X86: Record the initial APIC ID which identifies an APIC in M5.
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
2009-04-26 02:06:21 -07:00
Gabe Black
8d84f81e70 X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment. 2009-04-26 02:04:32 -07:00
Gabe Black
9d0fa27d09 SPARC: Tighten up the clone system call and SPARCs copyRegs. 2009-04-24 23:11:21 -07:00
Steve Reinhardt
7c056e44e5 request: reorganize flags to group related flags together. 2009-04-23 06:44:32 -07:00