Commit graph

4717 commits

Author SHA1 Message Date
Gabe Black
af1e8d2d40 Fixing the extended twin format to go with the new isa parser interface.
--HG--
extra : convert_revision : f41183cfa011b21e7ab8cbcdef0ac1d464692362
2006-12-18 18:17:30 -05:00
Nathan Binkert
0e78386874 Fix unittest compiles
--HG--
extra : convert_revision : 1163437081e1f1eab3f4512d04317dc94a673b9b
2006-12-18 14:08:42 -08:00
Nathan Binkert
9b40a13728 cast chars to int when we want to print integers so we get a number
instead of a character

--HG--
extra : convert_revision : 7bfa88ba23ad057b751eb01a80416d9f72cfe81a
2006-12-18 14:07:52 -08:00
Gabe Black
9e7dc34383 Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmem
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3

--HG--
extra : convert_revision : f17800685609d8353ec14676f45fbb123fc4e6c3
2006-12-18 12:19:30 -05:00
Ali Saidi
6841f863c5 move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD

src/arch/sparc/isa/decoder.isa:
    move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
    Make QUAD_LDD asi ok to execute

--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
2006-12-18 03:37:52 -05:00
Steve Reinhardt
d19d7aa8a5 Minor cleanup of new snippet/subst code.
--HG--
extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
2006-12-17 23:09:36 -08:00
Steve Reinhardt
968048f56a Convert Alpha (and finish converting MIPS) to new
InstObjParam interface.

src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
    Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
    Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
    Add (read|write)MiscRegOperand calls to Alpha DynInst.

--HG--
extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-17 19:27:50 -08:00
Nathan Binkert
e65544b88b Nate's utility for compiling m5
--HG--
extra : convert_revision : 84b21f667736dfe07891323dcc810437ccb3c7c0
2006-12-17 18:58:50 -08:00
Nathan Binkert
2d09f30a6d Utilities for doing a format check for some elements of proper
m5 style and fixing whitespace.  For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.

--HG--
extra : convert_revision : d0591663c028a388635fc71c6c1d31f700748cf6
2006-12-17 18:58:05 -08:00
Gabe Black
c3ec52346b Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
    Hand Merge

--HG--
extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
2006-12-17 11:55:24 -05:00
Gabe Black
81996f855a Compilation fixes.
--HG--
extra : convert_revision : 4932ab507580e0c9f7012398e71921ce58fc3c4e
2006-12-17 11:16:04 -05:00
Gabe Black
729dbb60e9 Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
    Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.

--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
2006-12-17 11:15:37 -05:00
Gabe Black
c299c2562b Started removing "CodeBlock" objects from the mips isa description.
--HG--
extra : convert_revision : 2e174ecfce8c86732e1addfc23e961429b86a570
2006-12-17 10:54:17 -05:00
Gabe Black
220e99a29b Compilation fix after messy merge.
--HG--
extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
2006-12-17 10:53:10 -05:00
Gabe Black
91b56d03fc Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : c8718b3df72b8c951c24742e8ce517a93bc23fe9
2006-12-16 12:55:55 -05:00
Gabe Black
c9f18981f9 Merge zizzer:/bk/sparcfs/
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : 2764b356ef01d1fcb6ed272e4ef96179cd651d4e
2006-12-16 12:55:15 -05:00
Gabe Black
b9d069167c Support for twin loads.
src/arch/sparc/isa/decoder.isa:
    Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
    Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
    Comment explaining twin load operands.

--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
2006-12-16 12:54:28 -05:00
Gabe Black
fe73760388 Compiler error fix.
--HG--
extra : convert_revision : 39e2638a10bf3e821e8f3d4d8c664008c98fc921
2006-12-16 12:53:01 -05:00
Gabe Black
9d0ca61b7e Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-16 11:35:40 -05:00
Gabe Black
f4f00c5ae9 Switch the endianness of data that's forwarded. This is the same sort of problem that was happening when stores went all the way to memory and back.
--HG--
extra : convert_revision : 09fece7ae934f542e51046d33505df3f7ec0b919
2006-12-16 09:35:09 -05:00
Gabe Black
96e5086c81 Make fetch detect when a branch is happening, rather than trying to compute when.
--HG--
extra : convert_revision : 1a8edc004570abb48e6c4cdf1b43c5699866838e
2006-12-16 09:34:20 -05:00
Gabe Black
a6eb16adb4 Accidently "cleaned" away the NPC parameter to the constructor.
--HG--
extra : convert_revision : 46670ee86000dfb171d327eb8f58555a4afb2360
2006-12-16 07:47:33 -05:00
Gabe Black
f410d5f4e0 Don't have "predict" set the predicted target of the instruction. Do that explicitly when you use predict.
--HG--
extra : convert_revision : 8b613bb365b31ffaef1cea9fd789abe46219bdcf
2006-12-16 07:39:44 -05:00
Gabe Black
569e0e883b Add in constants which let you explicitly check if endian conversion would do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move.
--HG--
extra : convert_revision : 4c904c964678529c72b8f1044dfcb400604f6654
2006-12-16 07:37:33 -05:00
Gabe Black
c6944e320c Add in capability to return to unblocking after a squash. This is needed because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer.
--HG--
extra : convert_revision : 7308eda27f4366348cf5fce71ddfa4b217bc172d
2006-12-16 07:35:56 -05:00
Gabe Black
244506ae12 Make sure endian conversion is done on the memory data when it's just set to an existing buffer.
--HG--
extra : convert_revision : 5a890091b6a31b5414acbf68f19e28d7122a98d7
2006-12-16 07:34:34 -05:00
Gabe Black
6413b74e4f Make the decoder use the new setup in the dyninsts for branch prediction.
--HG--
extra : convert_revision : 9a6d6c93e5b40a55774891df54d290ff557b322c
2006-12-16 07:33:08 -05:00
Gabe Black
37b9966eb4 Made branch delay slots get squashed, and passed back an NPC and NNPC to start fetching from.
--HG--
extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
2006-12-16 07:32:06 -05:00
Gabe Black
4d66ddbe35 Added a predicted NPC field, explicitly stored whether the instruction was predicted taken or not.
--HG--
extra : convert_revision : ba668af302ca4d8a3a032e907d5058e1477f462a
2006-12-16 07:22:19 -05:00
Gabe Black
181f4f32f6 Made changes to CWP be non speculative.
--HG--
extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
2006-12-16 07:10:58 -05:00
Gabe Black
6aa06a26b7 Changes to the isa_parser and affected files to fix an indexing problem with split execute instructions and miscregs aliasing with integer registers.
src/arch/isa_parser.py:
    Rearranged things so that classes with more than one execute function treat operands properly.
    1. Eliminated the CodeBlock class
    2. Created a SubOperandList
    3. Redefined how InstObjParams is constructed

    To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.

    Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
    Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.

--HG--
extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-16 07:10:04 -05:00
Lisa Hsu
4da37bcd1b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
2006-12-15 18:07:39 -05:00
Lisa Hsu
956e673c55 Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 68e9bb607fbeb1ed0ea4192411e804dc8e6ddd95
2006-12-15 18:02:23 -05:00
Lisa Hsu
385a3ff054 small change to eliminate address range overlap.
--HG--
extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
2006-12-15 17:58:20 -05:00
Lisa Hsu
551ba56ae2 little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.

src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
    Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
    pioSize indicates SIZE, not a mask

--HG--
extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
2006-12-15 17:55:47 -05:00
Lisa Hsu
991146218d Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
2006-12-15 13:27:53 -05:00
Lisa Hsu
b93b32ec33 Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
2006-12-15 13:06:37 -05:00
Lisa Hsu
573d59441e some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode

src/arch/sparc/miscregfile.cc:
    fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
    fix for build
src/cpu/exetrace.cc:
    wrap this variable between FULL_SYSTEM #ifs

--HG--
extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
2006-12-15 13:05:46 -05:00
Lisa Hsu
fbc796b347 loadstore.isa:
this privilegedString is never used

--HG--
extra : convert_revision : 5e6881d467792b670e0009cee8d5e96bc7a79a95
2006-12-15 13:01:06 -05:00
Lisa Hsu
9a4370ec3b tlb.cc:
fix namespace indentations

src/arch/alpha/tlb.cc:
    fix namespace indentations

--HG--
extra : convert_revision : 327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
2006-12-15 12:58:02 -05:00
Ali Saidi
4943d58272 Use my range_map to speed up findPort() in the bus. The snoop code could still use some work.
--HG--
extra : convert_revision : ba0a68bd378d68e4ebd80a101b965d36c8be1db9
2006-12-15 01:49:41 -05:00
Ali Saidi
5e70511bff Optimized the TLB translations with some caching
--HG--
extra : convert_revision : f79f863393f918ff9363b2c261f8c0dfec64312e
2006-12-15 01:48:09 -05:00
Ali Saidi
fa4293af33 flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff

src/arch/sparc/asi.cc:
    flesh out twinx asis
src/arch/sparc/miscregfile.cc:
    fix TICK register reads
src/arch/sparc/tlb.cc:
    reduce the number of readmiscreg accesses,
    implement tsb pointer stuff

--HG--
extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
2006-12-14 19:01:21 -05:00
Steve Reinhardt
d172e1576a Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).

--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-12-13 22:04:36 -08:00
Lisa Hsu
a10eff03a5 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 8cf3e824e4892249b12ed0fd92bb310748b18fa2
2006-12-13 17:52:24 -05:00
Lisa Hsu
98bb1c62b3 fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG--
extra : convert_revision : 4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
2006-12-13 17:51:28 -05:00
Lisa Hsu
0fa30e579e Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
2006-12-13 14:33:59 -05:00
Lisa Hsu
a983c4968c Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : c6d174716641f0b8286b8478bcb9053b3eec54e3
2006-12-13 14:33:32 -05:00
Lisa Hsu
5d42fd836b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-12 21:19:51 -05:00
Gabe Black
90907f6b3c Merge zizzer:/bk/newmem/
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
2006-12-12 18:10:00 -05:00