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6aa06a26b7
src/arch/isa_parser.py:
Rearranged things so that classes with more than one execute function treat operands properly.
1. Eliminated the CodeBlock class
2. Created a SubOperandList
3. Redefined how InstObjParams is constructed
To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.
Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.
--HG--
extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
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| README | ||
| RELEASE_NOTES | ||
| SConstruct | ||
This is release 2.0_beta (patch 1) of the M5 simulator. For detailed information about building the simulator and getting started please refer to http://www.m5sim.org. Specific pages of interest are: http://www.m5sim.org/wiki/index.php/Compiling_M5 http://www.m5sim.org/wiki/index.php/Running_M5 Short version: 1. If you don't have SCons version 0.96.91 or newer, get it from http://wwww.scons.org. 2. If you don't have SWIG version 1.3.28 or newer, get it from http://wwww.swig.org. 3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This will build the debug version of the m5 binary (m5.debug) for the Alpha syscall emulation target, and run the quick regression tests on it. If you have questions, please send mail to m5-users@m5sim.org WHAT'S INCLUDED (AND NOT) ------------------------- The basic source release includes these subdirectories: - m5: - src: source code of the m5 simulator - tests: regression tests - ext: less-common external packages needed to build m5 - system/alpha: source for Alpha console and PALcode To run full-system simulations, you will need compiled console, PALcode, and kernel binaries and one or more disk images. These files are collected in a separate archive, m5_system.tar.bz2. This file can he downloaded separately. M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux and FreeBSD bootdisks, but we are unable to distribute bootable disk images of Tru64 Unix. If you have a Tru64 license and are interested in obtaining disk images, contact us at m5-dev@eecs.umich.edu.