Commit graph

11589 commits

Author SHA1 Message Date
Michael LeBeane
2ae4cce393 configs: add command-line option to stop debug output
This patch adds a --debug-end flag to main.py so that debug output can be
stoped at a specified tick, while allowing the simulation to continue. It is
useful in situations where you would like to produce a trace for a region of
interest while still collecting stats for the entire run. This is in contrast
to the currently existing --debug-break flag, which terminates the simulation
at the tick.
2016-02-13 12:36:43 -05:00
Michael LeBeane
8d923c7380 syscall_emul: Implement clock_getres() system call
This patch implements the clock_getres() system call for arm and x86 in linux
SE mode.
2016-02-13 12:33:07 -05:00
Andreas Hansson
c6cede244b stats: Update stats to reflect changes to cache and crossbar 2016-02-10 04:08:27 -05:00
Andreas Hansson
83a5977481 mem: Be less conservative in clearing load locks in the cache
Avoid being overly conservative in clearing load locks in the cache,
and allow writes to the line if they are from the same context. This
is in line with ALPHA and ARM.
2016-02-10 04:08:25 -05:00
Andreas Hansson
92f021cbbe mem: Move the point of coherency to the coherent crossbar
This patch introduces the ability of making the coherent crossbar the
point of coherency. If so, the crossbar does not forward packets where
a cache with ownership has already committed to responding, and also
does not forward any coherency-related packets that are not intended
for a downstream memory controller. Thus, invalidations and upgrades
are turned around in the crossbar, and the memory controller only sees
normal reads and writes.

In addition this patch moves the express snoop promotion of a packet
to the crossbar, thus allowing the downstream cache to check the
express snoop flag (as it should) for bypassing any blocking, rather
than relying on whether a cache is responding or not.
2016-02-10 04:08:25 -05:00
Andreas Hansson
f84ee031cc mem: Align cache behaviour in atomic when upstream is responding
Adopt the same flow as in timing mode, where the caches on the path to
memory get to keep the line (if present), and we use the
responderHadWritable flag to determine if we need to forward the
(invalidating) packet or not.
2016-02-10 04:08:24 -05:00
Andreas Hansson
986214f181 mem: Align how snoops are handled when hitting writebacks
This patch unifies the snoop handling in case of hitting writebacks
with how we handle snoops hitting in the tags. As a result, we end up
using the same optimisation as the normal snoops, where we inform the
downstream cache if we encounter a line in Modified (writable and
dirty) state, which enables us to avoid sending out express snoops to
invalidate any Shared copies of the line. A few regressions
consequently change, as some transactions are sunk higher up in the
cache hierarchy.
2016-02-10 04:08:24 -05:00
Andreas Hansson
fbdeb60316 mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.

The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
2016-02-10 04:08:24 -05:00
Curtis Dunham
bead7f249a scons: always generate sim/tags.cc
Due to insufficient build deps, the checkpoint tags might not get
updated; this commit solves this. Due to the uncommon nature of the
build target, regenerating tags.cc is a fairly clean solution. Since
SCons hashes file contents, it won't recompile anything unless a new
checkpoint upgrader is actually added.

--HG--
extra : amend_source : ed3879da7668554693f697076deaf5029cc9b954
2016-02-08 13:39:45 -06:00
Alexandru Dutu
0f27d70e90 x86: revamp cmpxchg8b/cmpxchg16b implementation
The previous implementation did a pair of nested RMW operations,
which isn't compatible with the way that locked RMW operations are
implemented in the cache models.  It was convenient though in that
it didn't require any new micro-ops, and supported cmpxchg16b using
64-bit memory ops.  It also worked in AtomicSimpleCPU where
atomicity was guaranteed by the core and not by the memory system.
It did not work with timing CPU models though.

This new implementation defines new 'split' load and store micro-ops
which allow a single memory operation to use a pair of registers as
the source or destination, then uses a single ldsplit/stsplit RMW
pair to implement cmpxchg.  This patch requires support for 128-bit
memory accesses in the ISA (added via a separate patch) to support
cmpxchg16b.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
5200e04e92 arch, x86: add support for arrays as memory operands
Although the cache models support wider accesses, the ISA descriptions
assume that (for the most part) memory operands are integer types,
which makes it difficult to define instructions that do memory accesses
larger than 64 bits.

This patch adds some generic support for memory operands that are arrays
of uint64_t, and specifically a 'u2qw' operand type for x86 that is an
array of 2 uint64_ts (128 bits).  This support is unused at this point,
but will be needed shortly for cmpxchg16b.  Ideally the 128-bit SSE
memory accesses will also be rewritten to use this support.

Support for 128-bit accesses could also have been added using the gcc
__int128_t extension, which would have been less disruptive.  However,
although clang also supports __int128_t, it's still non-standard.
Also, more importantly, this approach creates a path to defining
256- and 512-byte operands as well, which will be useful for eventual
AVX support.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
f5343df1e1 arch: get rid of dummy var init
MemOperand variables were being initialized to 0
"to avoid 'uninitialized variable' errors" but these
no longer seem to be a problem (with the exception of
one use case in POWER that is arguably broken and
easily fixed here).

Getting rid of the initialization is necessary to
set up a subsequent patch which extends memory
operands to possibly not be scalars, making the
'= 0' initialization no longer feasible.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
92b750d5ef syscall_emul: fix bug in aux vector initialization
Writing 16 bytes from an 8-byte source value is a bad idea.
This doesn't appear to have broken anything, but showed up
as spurious differences when tracediffing runs.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
f6b828d068 style: eliminate explicit boolean comparisons
Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.

Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>>        DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>>            "EXPECT_FALSE(" #expr ")", (expr) == false)<<
2016-02-06 17:21:20 -08:00
Steve Reinhardt
2d91e741e8 x86: create function to check miscreg validity
In the process of trying to get rid of an '== false' comparison,
it became apparent that a slightly more involved solution was
needed.  Split this out into its own changeset since it's not
a totally trivial local change like the others.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
4e65e25e25 util: fix apparent statetrace bug
In the process of trying to eliminate boolean comparisons,
I ran across this statement that appears to be a bug
(should have been an assignment).
2016-02-06 17:21:20 -08:00
Steve Reinhardt
2728f7bd81 util: added line length and boolean comparison style checkers
Added checkers for line length and boolean comparisons
(== true/== false) to the style script.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
5592798865 style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06 17:21:19 -08:00
Steve Reinhardt
dc8018a5c3 style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06 17:21:18 -08:00
Steve Reinhardt
c8c82f09a2 util: clean up and extend style checker
Added a new Verifier object to check for and fix spacing
between if/while/for and following paren.

Restructured Verifier class to make it easier to add
new subclasses, particularly by using a global list of
verifiers to auto-generate command line options and
simplify the invocation loop.
2016-02-06 17:21:18 -08:00
Steve Reinhardt
9979355539 util: delete old unused style-checking scripts
The functions in these scripts were apparently folded into style.py but the
old scripts were orphaned without being deleted.  Get rid of them so their
existence is no longer confusing.
2016-02-06 17:21:18 -08:00
Mohammad Alian
24da47cf96 dist, dev: add an ethernet switch model 2016-02-06 13:33:34 -05:00
Steve Reinhardt
ce35c06c6e stats: update EIO stats for recent changes 2016-02-06 01:35:03 -05:00
Curtis Dunham
b4282af318 ext: fix SST connector
Should work with SST 5.1 and trunk as of right now.
2016-02-04 16:57:59 -06:00
Curtis Dunham
fe32b40269 ext: remove redundant parameter in example SST+gem5 test
The SST connector automatically adds --initialize-only to the gem5
"command line" (as it should); the config script doesn't need it.
2016-01-29 17:47:15 -06:00
Andreas Sandberg
b99fea78a6 ext: Update NoMali to external rev f08e0a5
Update NoMali from external revision 9adf9d6 to f08e0a5 and bring in
the following changes:

f08e0a5 Add support for tracking address space state
f11099e Fix job slot register handling when running new jobs
b28c98e api: Add a reset callback
29ac4c3 tests: Update gitignore to cover all future test cases
1c6b893 Propagate reset calls to all job slots
8f8ec15 Remove redundant reg vector in MMU
85d90d2 tests: Fix incorrect extern declaration
2016-01-29 12:14:21 +00:00
Tony Gutierrez
1285d639eb stats: update stats to after GPU checkin 2016-01-22 10:42:13 -05:00
Brad Beckmann
dcd8eeec3b ruby: removed Write_Only AccessPermission 2016-01-22 10:42:12 -05:00
Brad Beckmann
97a5e5b25e ruby: changed all references to numCPs to num-cp 2016-01-22 10:42:12 -05:00
David Hashe
698866d461 ruby: split CPU and GPU latency stats 2015-07-20 09:15:18 -05:00
Tony Gutierrez
1a7d3f9fcb gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
Tony Gutierrez
28e353e040 mem: write combining for ruby protocols
This patch adds support for write-combining in ruby.
2016-01-19 14:05:03 -05:00
Tony Gutierrez
d658b6e1cc * * *
mem: support for gpu-style RMWs in ruby

This patch adds support for GPU-style read-modify-write (RMW) operations in
ruby. Such atomic operations are traditionally executed at the memory controller
(instead of through an L1 cache using cache-line locking).

Currently, this patch works by propogating operation functors through the memory
system.
2016-01-19 13:57:50 -05:00
Blake Hechtman
34fb6b5e35 mem: misc flags for AMD gpu model
This patch add support to mark memory requests/packets with attributes defined
in HSA, such as memory order and scope.
2015-07-20 09:15:18 -05:00
Steve Reinhardt
b7ea2bc705 sim: fix redundant --debug-start help string
Just changes the metavar for --debug-start from TIME
to TICK in cset 72046b9b3323 and didn't notice that the
comment "must be in ticks" is now redundant.
2016-01-17 19:18:49 -08:00
Steve Reinhardt
1b6355c895 cpu. arch: add initiateMemRead() to ExecContext interface
For historical reasons, the ExecContext interface had a single
function, readMem(), that did two different things depending on
whether the ExecContext supported atomic memory mode (i.e.,
AtomicSimpleCPU) or timing memory mode (all the other models).
In the former case, it actually performed a memory read; in the
latter case, it merely initiated a read access, and the read
completion did not happen until later when a response packet
arrived from the memory system.

This led to some confusing things, including timing accesses
being required to provide a pointer for the return data even
though that pointer was only used in atomic mode.

This patch splits this interface, adding a new initiateMemRead()
function to the ExecContext interface to replace the timing-mode
use of readMem().

For consistency and clarity, the readMemTiming() helper function
in the ISA definitions is renamed to initiateMemRead() as well.
For x86, where the access size is passed in explicitly, we can
also get rid of the data parameter at this level.  For other ISAs,
where the access size is determined from the type of the data
parameter, we have to keep the parameter for that purpose.
2016-01-17 18:27:46 -08:00
Steve Reinhardt
707275265f cpu: remove unnecessary data ptr from O3 internal read() funcs
The read() function merely initiates a memory read operation; the
data doesn't arrive until the access completes and a response packet
is received from the memory system.  Thus there's no need to provide
a data pointer; its existence is historical.

Getting this pointer out of this internal o3 interface sets the
stage for similar cleanup in the ExecContext interface.  Also
found that we were pointlessly setting the contents at this pointer
on a store forward (the useful memcpy happens just a few lines
below the deleted one).
2016-01-17 18:27:46 -08:00
Steve Reinhardt
e595d9cccb arch: don't call *Timing functions from *Atomic versions
The readMemAtomic/writeMemAtomic helper functions were calling
readMemTiming/writeMemTiming respectively.  This is functionally
correct, since the *Timing functions are doing the same access
initiation operation as the *Atomic functions (just that the
*Atomic versions also complete the access in line).  It also
provides for some (very minimal) code reuse.  Unfortunately,
it's potentially pretty confusing, since it makes it look like
the atomic accesses are somehow being converted to timing
accesses.  It also gets in the way of specializing the timing
interface (as will be done in a future patch).
2016-01-17 18:27:46 -08:00
Steve Reinhardt
fb0383bc72 arch: get rid of unused LargestRead typedef 2016-01-17 18:27:46 -08:00
Steve Reinhardt
28a0e5a165 sim: don't ignore SIG_TRAP
By ignoring SIG_TRAP, using --debug-break <N> when not connected to
a debugger becomes a no-op.  Apparently this was intended to be a
feature, though the rationale is not clear.

If we don't ignore SIG_TRAP, then using --debug-break <N> when not
connected to a debugger causes the simulation process to terminate
at tick N.  This is occasionally useful, e.g., if you just want to
collect a trace for a specific window of execution then you can combine
this with --debug-start to do exactly that.

In addition to not ignoring the signal, this patch also updates
the --debug-break help message and deletes a handful of unprotected
calls to Debug::breakpoint() that relied on the prior behavior.
2016-01-17 18:27:46 -08:00
Steve Reinhardt
fcfe6e798d stats: update SPARC FS stats
The fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic test was
broken for so long that, now that it's working again, the stats
output is out of date.  This changeset updates the outputs, on
the assumption that the stats changes are all valid differences
due to other changes made while it was broken.
2016-01-17 21:13:29 -05:00
Andreas Sandberg
745f8229f6 dev, arm: Add a platform with support for both aarch32 and aarch64
Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:

  * Automatic PCI interrupt assignment
  * PCI interrupts allocated in a contiguous range.
  * Automatic boot loader selection (32-bit / 64-bit)
  * Cleaner memory map where gem5-specific devices live in CS5 which
    isn't used by current Versatile Express platforms.
  * No fake devices. Devices that were previously faked will be
    removed from the device tree instead.
  * Support for 510 GiB contiguous memory
2016-01-15 11:30:13 +00:00
Andreas Sandberg
6d058a63b0 dev, arm: Add support for automatic PCI interrupt routing
Add support for automatic PCI interrupt routing using a device's ID on
the PCI bus. Our current DTBs typically tell the kernel that we do
this or something similar when declaring the PCI controller. This
changeset adds an option to make the simulator behave in the same way.

Interrupt routing can be selected by setting the int_policy parameter
in the GenericArmPciHost. The following values are supported:

  * ARM_PCI_INT_STATIC: Use the old static routing policy using the
    interrupt line from a device's configurtion space.

  * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an
    interrupt in the GIC. The interrupt is computed as:

    gic_int = int_base + (pci_dev % int_count)

  * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to
    an interrupt in the GIC. The PCI specification reserves pin ID 0
    for devices without interrupts, the interrupt therefore computed
    as:

    gic_int = int_base + ((pin - 1) % int_count)
2016-01-15 11:30:06 +00:00
Steve Reinhardt
8406a54907 mem: fix bug in packet access endianness changes
The new Packet::setRaw() method incorrectly still contained
an htog() conversion.  As a result, calls to the old set()
method (now defined as setRaw(htog(v))) underwent two htog
conversions, which breaks things when htog() is not a no-op.

Interestingly the only test that caught this was a SPARC
boot test, where an IsaFake device with a non-zero return
value was getting swapped twice resulting in a register
getting loaded with 0x100000000000000 instead of 1.
(Good reason for keeping SPARC around, perhaps?)
2016-01-11 16:20:38 -05:00
Andreas Hansson
12eb034378 scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
2016-01-11 05:52:20 -05:00
Andreas Hansson
7661f1c2bf ext: Replace gzstream with iostream3 from zlib to avoid LGPL
This patch replaces the gzstream zlib wrapper with the iostream3
wrapper provided as part of zlib contributions. The main reason for
the switch is to avoid including LGPL in the default gem5
build. iostream3 is provided under a more permissive license:

The code is provided "as is", with the permission to use, copy,
modify, distribute and sell it for any purpose without fee.
2016-01-11 05:52:18 -05:00
Andreas Hansson
c965ca96cc configs: Fix inheritance of HMCSystem and cleanup spacing
Minor fix to ensure the HMCSystem can actually be instantiated
(SimObject cannot be created). Also address some spacing issues.
2016-01-11 05:52:17 -05:00
Gabor Dozsa
64ca31976f config: Updates for distributed gem5 simulations 2016-01-07 16:33:47 -06:00
Gabor Dozsa
5dec4e07b8 dev: Distributed Ethernet link for distributed gem5 simulations
Distributed gem5 (abbreviated dist-gem5) is the result of the
convergence effort between multi-gem5 and pd-gem5 (from Univ. of
Wisconsin). It relies on the base multi-gem5 infrastructure for packet
forwarding, synchronisation and checkpointing but combines those with
the elaborated network switch model from pd-gem5.

--HG--
rename : src/dev/net/multi_etherlink.cc => src/dev/net/dist_etherlink.cc
rename : src/dev/net/multi_etherlink.hh => src/dev/net/dist_etherlink.hh
rename : src/dev/net/multi_iface.cc => src/dev/net/dist_iface.cc
rename : src/dev/net/multi_iface.hh => src/dev/net/dist_iface.hh
rename : src/dev/net/multi_packet.hh => src/dev/net/dist_packet.hh
2016-01-07 16:33:47 -06:00
Gabor Dozsa
e677494260 pseudo inst,util: Add optional key to initparam pseudo instruction
The key parameter can be used to read out various config parameters from
within the simulated software.
2016-01-07 16:33:47 -06:00