flags for their functions (e.g. OS::OSFlags::TG_MAP_ANONYMOUS)...
arch/alpha/tru64/process.cc:
sim/syscall_emul.hh:
Add OSFlags to code
arch/mips/isa/decoder.isa:
slight decoder changes (more stylistic then anything)
arch/mips/isa/formats/util.isa:
spacing
arch/mips/isa_traits.hh:
add OSFlags struct to MipsISA namespace. The OS classes then use these OSFlags to access architecture-specific and OS-specific
flags for their functions
kern/linux/linux.hh:
remove constant placement ... define OSFlags in linux.hh
kern/tru64/tru64.hh:
define OSFlags in tru64
--HG--
extra : convert_revision : 59be1036eb439ca4ea1eea1d3b52e508023de6c9
arch/mips/isa/bitfields.isa:
add RS_SRL bitfield ...these must be set to 0 for a SRL instruction
arch/mips/isa/decoder.isa:
Make unimplemented instructions Fail instead of just Warn
Edits to SRA & SRAV instructions
Implement CFC1 instructions
Unaligned Memory Access Support (Maybe Not fully functional yet)
Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions)
arch/mips/isa/formats/branch.isa:
Fix disassembly
arch/mips/isa/formats/int.isa:
Add sign extend Immediate and zero extend Immediate to Int class.
Probably a bit unnecessary in the long run since these manipulations could
be done in the actually instruction instead of keep a int value
arch/mips/isa/formats/mem.isa:
Comment/Remove out split-memory access code... revisit this after SimpleCPU works
arch/mips/isa/formats/unimp.isa:
Add inst2string function to Unimplemented panic. PRints out the instruction
binary to help in debuggin
arch/mips/isa/formats/unknown.isa:
define inst2string function , use in unknown disassembly and panic function
arch/mips/isa/operands.isa:
Make "Mem" default to a unsigned word since this is MIPS32
arch/mips/isa_traits.hh:
change return values to 32 instead of 64
arch/mips/linux_process.cc:
assign some syscalls to the right functions
cpu/static_inst.hh:
more debug functions for MIPS (these will be move to the mips directory soon)
mem/page_table.cc:
mem/page_table.hh:
toward a better implementation for unaligned memory access
mem/request.hh:
NO ALIGN FAULT flag added to support unaligned memory access
sim/syscall_emul.cc:
additional SyscallVerbose comments
--HG--
extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c
arch/mips/isa/decoder.isa:
arch/mips/isa_traits.hh:
sim/syscall_emul.cc:
make syscall instruction functional
arch/mips/linux_process.cc:
add all MIPS/Linux syscalls to descriptor list
--HG--
extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
before getting in a infinite loop. It actually "tries" to syscall too, but syscalls
aren't implemented just yet
arch/mips/faults.cc:
more descriptive names for faults (will help future users as well as me!)
arch/mips/isa/base.isa:
make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest
arch/mips/isa/decoder.isa:
FIX LW/SW Bug!!!! I was actually loading a byte instead of a word
FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction
FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly
base/loader/elf_object.cc:
change back to original way
base/loader/elf_object.hh:
change back to original!
--HG--
extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
SConscript:
Separate Alpha EIO from syscall building for other architectures
arch/isa_specific.hh:
change MIPS constant to 34k
arch/mips/isa/decoder.isa:
Allow sll,ssnop,nop, and ehb to be determined through decoder using
the different types of default cases
arch/mips/isa/formats/branch.isa:
Delete debug code
arch/mips/isa/formats/noop.isa:
add a Nop format
arch/mips/isa_traits.hh:
use constants instead of enums
arch/mips/process.cc:
point to the correct header file
cpu/simple/cpu.cc:
Output the actual fault name
sim/process.cc:
Inititalize NNPC
--HG--
extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
arch/alpha/isa_traits.hh:
used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
so other archs. can use SimpleCPU
arch/mips/SConscript:
dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
Change Faults to new format
arch/mips/isa/decoder.isa:
Fix readMiscReg access
Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
create copyMiscRegs function...
delete useless code
arch/mips/isa_traits.hh:
clean up for build
arch/mips/linux_process.cc:
mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
new argument for linux process
arch/mips/process.cc:
add system
arch/mips/process.hh:
add system variable
cpu/cpu_exec_context.cc:
Change AlphaISA to TheISA
cpu/exec_context.hh:
add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
include isa_traits for namespace declariation
cpu/simple/cpu.hh:
PC & NPC access/modify functions
arch/mips/utility.hh:
file needed for compile
--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
Redo format for Branches and Jumps ( Must update NNPC not NPC )
Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!
arch/mips/isa/decoder.isa:
Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
define clear_exe_inst_hazards for later use
--HG--
extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
Now, must create g++ compilable code ...
arch/mips/isa/decoder.isa:
missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
rearranged #include
arch/mips/isa/formats/branch.isa:
add Branch Likely and Unconditional format
arch/mips/isa/formats/int.isa:
move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
change Alpha to Mips in noop.isa
--HG--
extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424
arch/mips/isa/decoder.isa:
CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
include util.isa
arch/mips/isa/formats/branch.isa:
erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
util.isa
--HG--
extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
=================================================
-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.
--HG--
extra : convert_revision : 4a26c72e4fa1f63b8689fe2631a7508daf660969
arch/mips/isa/decoder.isa:
Code for di,ei,seb,seh,clz,and clo ....
Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
Format Branch in MIPS similar to Alpha Format
--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
