can specify either independently.
python/m5/objects/Device.py:
io_bus is split out into pio_bus and dma_bus so that any device
can specify either independently.
dma_bus defaults to point to whatever pio_bus uses.
--HG--
extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
base/mysql.hh:
include mysql_version to get rid of that annoying mysql error.
make sure refcount is set in all constructors
base/pollevent.hh:
dev/ethertap.hh:
dev/pciconfigall.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
sim/param.cc:
fix for gcc 4
--HG--
extra : convert_revision : be626af2f40ca402818996ef27249ae256c63ef1
Doxyfile:
Turn on EXTRACT_ALL so we get full class hierarchy info.
base/range.hh:
cpu/o3/fetch.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
dev/ide_disk.cc:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
Fix doxygen issues.
--HG--
extra : convert_revision : 9e0e8d3510b35db201459b8a3211c5e6ad5f0bb4
base/socket.cc:
Make panic print a more worthwhile message
dev/tsunami.hh:
Change max number of tsunami cpus to be 64
dev/tsunamireg.h:
Add new registers and register blocks for 64 cpu tsunami
--HG--
extra : convert_revision : 3ceaaa998518ded8613bc64edc04cb9120fd3d15
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
dev/tsunami_cchip.hh:
clean up some comments
kern/linux/linux_syscalls.cc:
Cleaned up spacing of syscall numbers
kern/linux/linux_system.hh:
Added doxygen comments
--HG--
extra : convert_revision : 23ecdaa92a208458dd5c5d3c68ac9012ce2690da
dev/baddev.hh:
dev/pcidev.hh:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
Added doxygen comments
dev/pciconfigall.hh:
Added doxygen comments. Made the hlist of devices private and provided
members to modify the data.
dev/pcidev.cc:
updated for change in pciconfigall
dev/tsunami_pchip.cc:
Deleted commented out code we don't need
kern/linux/linux_syscalls.cc:
Simplified the number -> name conversion.
kern/linux/linux_syscalls.hh:
Removed StandardNumber and replaced with Number.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
LinuxSkipIdeDelay50msEvent was simply the same as the SkipFunc event,
so I removed it. Same with with LinuxSkipFuncEvent.
--HG--
extra : convert_revision : 1508c335f87d90373f5772f3a0407ea13e858d7e
are present
dev/tsunami_cchip.cc:
Only need to interrupt processors that are there
Move RTC interrupt code into a function
dev/tsunami_cchip.hh:
Make a RTC interrupt function, move variables out of public scope
dev/tsunami_io.cc:
Make a call to the RTC interrupt routine instead
--HG--
extra : convert_revision : 88113664d0e54a7dddc00ec11ff9b9d088232b31
dev/tsunami_cchip.cc:
Add support for IPI, making changes to read/write to MISC register
Particularly the IPREQ, IPINTR, and ITINTR subfields
dev/tsunami_cchip.hh:
Make an array to keep track of the number of outstanding IPI's,
Extend RTC to interrupt all processors, not just cpu0
dev/tsunami_io.cc:
Extend RTC to interrupt all present proccessors, not just cpu0
--HG--
extra : convert_revision : 0715cbf0abb06002c0fb0b05ef369304cdf75001
interrupt to use a different subnumber since both devices could
interrupt at the same time and we don't want to loose one.
dev/tsunami_cchip.cc:
rewrote interrupt code to handle interrupt mask clearing correctly
dev/tsunami_cchip.hh:
changed (post/clear)DRIR to use a interrupt number rather than a vecotr
dev/tsunami_io.cc:
updated for new post/clearDRIR calls
--HG--
extra : convert_revision : 5b39f5e15a66d5eb6e689e6ece62f99b5fa735ab
some sundry problems with new interface
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Fixed to use new FunctionalMemory interface
--HG--
extra : convert_revision : bee98e6285d92f28fafacf919ab06eaf333a9b56
dev/alpha_access.h:
removed my attempted hack to get console compling in linux
dev/tsunami.cc:
dev/tsunami.hh:
added pchip pointer to tsunami
dev/tsunami_cchip.cc:
made printing better
dev/tsunami_cchip.hh:
commented out back pointer for now, since the parser has issues with it
dev/tsunamireg.h:
added pchip registers
--HG--
extra : convert_revision : b4fceb7d08e757d9aaf37df8eb1bcd5ae29ce0da
