src/cpu/o3/lsq.hh:
Update to have LSQ work with only one dcache port for all LSQ Units. LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Update for LSQ to create dcache port instead of LSQUnits. Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.
--HG--
extra : convert_revision : 2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
Since se mode has a system, allow access to it
Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
Since se mode has a system, allow access to it
Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
Implement drain() support in devices
src/python/m5/config.py:
Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
memory mode information now contained in system object
--HG--
extra : convert_revision : 1389c77e66ee6d9710bf77b4306fb47e107b21cf
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/test.py:
Hand merge.
--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
src/SConscript:
It's no longer "ALPHA_ISA". I don't think we meant to leave out the EIO sources.
--HG--
extra : convert_revision : 1ca63ffb571d9021f1ced0bf0df1816b0b798edc
src/cpu/o3/commit_impl.hh:
Always set instruction. This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
Change serialization so it matches other CPU's output. Also fix up some indexing.
--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
configs/test/fs.py:
Pull a lot of the default options out of the config file now that they are in the Python objects themselves. Also merge this file with the single_fs.py, allowing one file to be used for both. Previously they differed only by the system they instantiated.
configs/test/test.py:
Initial stab at consolidating configuration files so they aren't redundant between the regression tests and the simple examples.
--HG--
extra : convert_revision : e8ae3de5a6d8864831f21089d4fdb8ec690e4731
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
Push more default options to the Python object level as they are rarely changed.
--HG--
extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
src/cpu/o3/fetch_impl.hh:
Hand merge.
--HG--
extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
src/python/m5/main.py:
Add a command line option to invoke pdb on your script
--HG--
extra : convert_revision : ef5a2860bd3f6e479fa80eccaae0cb5541a20b50
Now to work on caches in FS, first steps:
1) LL/SC support (Top Level Cache Hooks)
2) Snooping in the bus (CSHR's for DMA Invalidates)
--HG--
extra : convert_revision : b4e7984712f7dcd42649070c5ca538c87461e179
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).
src/cpu/o3/fetch_impl.hh:
Fix ordering issue with squashed Icache Fetches and Static data in packet.
--HG--
extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
src/python/m5/main.py:
Don't allow interspersed arguments, it messes things up
--HG--
extra : convert_revision : 8f1bcf4391f570741d92bf5420879862a48f6016
configs/test/fs.py:
configs/test/test.py:
update for the new way that m5 deals with options
src/python/SConscript:
Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the
python stuff.
src/python/m5/__init__.py:
redo the way options work.
Move them all to main.py
src/sim/main.cc:
Migrate more functionality for main() into python.
Namely option parsing
src/python/m5/attrdict.py:
A dictionary object that overrides attribute access to
do item access.
src/python/m5/main.py:
The new location for M5's option parsing, and the main()
routine to set up the simulation.
--HG--
extra : convert_revision : c86b87a9f508bde1994088e23fd470c7753ee4c1
src/mem/cache/base_cache.cc:
If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
Actually save the address, otherwise we can't match MSHR's
--HG--
extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
src/cpu/SConscript:
Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
Remove old code.
src/cpu/o3/commit_impl.hh:
Remove old unused code.
--HG--
extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
Support Ron's recent port changes. Also support handling faults in SE.
--HG--
extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
src/cpu/checker/cpu.hh:
Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
Add ports to the parameters.
--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
src/sim/main.cc:
src/sim/serialize.cc:
src/sim/serialize.hh:
Take in the directory name when checkpointing.
--HG--
extra : convert_revision : 040e828622480f1051e2156f4439e24864c38d45
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : be8b295ebf54a7c6bf720a20ab6aa9f02aee8060
On the way towards multi-level caches (L2)
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Fix address range calculation. Still need bus to handle snoop ranges.
--HG--
extra : convert_revision : 800078d88aab5e563f4a9bb599f91cd44f36e625
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : f97469b7d19c82deb3d068f80546d729757c25e3
Still, there is a problem with the LSQ and indexing out of range in the buffer.
I havent nailed down the fix yet, but it's coming ...
src/cpu/o3/commit_impl.hh:
add space to DPRINT
src/cpu/o3/cpu.cc:
add newline to DPRINT
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
Each thread needs it's own squashedSeqNum for the case where they are both squashing at the same time and they dont
write over each other's squash number.
--HG--
extra : convert_revision : 2155421a8b5b20e4544eea3d3c53d3e715465fa6
src/cpu/o3/cpu.cc:
Fix up keeping proper state when switched out and drained.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Keep track of the event we use to schedule fetch initially and upon resume. We may have to cancel the event if the CPU is switched out.
--HG--
extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
configs/test/test.py:
Update to use new cpu getPort functionality
src/cpu/base.cc:
Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
Make sure the cache recognizes all port names
--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 90717b492139428e0c48be35a6bda45960c61086
Major thing was to not execute commit if there are no active threads in CPU.
src/cpu/o3/alpha/thread_context.hh:
call deallocate instead of deallocateContext
src/cpu/o3/commit_impl.hh:
dont run commit stage if there are no instructions
src/cpu/o3/cpu.cc:
add deallocate event, deactivateThread function, and edit deallocateContext.
src/cpu/o3/cpu.hh:
add deallocate event and add optional delay to deallocateContext
src/cpu/o3/thread_context.hh:
optional delay for deallocate
src/cpu/o3/thread_context_impl.hh:
edit DPRINTFs to say Thread Context instead of Alpha TC
src/cpu/thread_context.hh:
optional delay
src/sim/syscall_emul.hh:
name stuff
--HG--
extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6
src/cpu/o3/commit_impl.hh:
Fix to clear drainPending variable on call to resume.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Support serializing and unserializing in the O3 CPU.
src/cpu/o3/lsq_impl.hh:
Be sure to say we have no stores to write back if the active thread list is empty.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
Slightly change how SimpleThread is used to copy from other ThreadContexts.
--HG--
extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121
