SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
Remove OOO CPU stuff.
arch/alpha/faults.hh:
Add fake memory fault. This will be removed eventually.
arch/alpha/isa_desc:
Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
Remove asid.
cpu/beta_cpu/comm.hh:
Remove global history field.
cpu/beta_cpu/commit.hh:
Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
Add debug function.
cpu/beta_cpu/decode_impl.hh:
Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
Extra forward declares added due to compile error.
--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
kern/linux/linux_system.cc:
calibrate delay starts three instructions after the symbol now.
--HG--
extra : convert_revision : f9c2bed3bca1f3394801fe7696cfff870443c204
Add support for hit under miss of a no allocate (It seems as though DMA reads to the same block happen close together, is this an artifact of the header/payload splitting)
Make sure to respond to all targets of a no_allocate request
--HG--
extra : convert_revision : a9d733f499face4039929524573ffc9500e93d83
Delay before singalling peer to make sure that the peer is ready
configs/boot/nat-netperf-server.rcS:
delay before singalling to make sure that the natbox is ready
configs/boot/nat-netperf-stream-client.rcS:
increase the number of tracked connections
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-smallb.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
increase the number of tracked connections
cleanup
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
delay before singalling to make sure that the natbox is ready
increase the number of tracked connections
cleanup
configs/boot/natbox-spec-surge.rcS:
delay before singalling to make sure that the natbox is ready
increase the number of tracked connections
--HG--
extra : convert_revision : 9faa5ec11c9c02fed3d1cff922ca42c41d364204
cpu/pc_event.cc:
Add a newline to the printout to clean up output
kern/linux/linux_system.cc:
Remove the die_if_kernel pc break event, it is being called when not the kernel and leads to unneeded printouts
--HG--
extra : convert_revision : c359532db31c961074894cc6c44c8452592caca8
can pass simulator specific options to the device driver.
dev/ns_gige.cc:
Add the m5 register and parameter to the ns83820 device model
so that we can pass simulator specific options to the device
driver.
dev/ns_gige.hh:
dev/ns_gige_reg.h:
Add the m5 register to the ns83820 device model
--HG--
extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09
arch/alpha/alpha_tru64_process.cc:
getdirent isn't implemented by cygwin. panic if this function is
executed. (It shouldn't be too much to emulate it using opendir,
readdir, etc.)
arch/alpha/pseudo_inst.cc:
Use lseek once and read instead pread.
base/intmath.hh:
we want int, long, and long long variations of FloorLog2 instead
of int32_t, int64_t. Otherwise, we leave one out.
base/socket.cc:
Fix define that seems to be for apple
sim/serialize.cc:
don't use the intXX_t stuff, instead, use the real types
so we're sure that we cover all of them.
--HG--
extra : convert_revision : 9fccaff583100b06bbaafd95a162c4e19beed59e
(plus some small fixes).
python/m5/config.py:
Hacks to allow multiplication on Frequency/Latency-valued proxies.
Provide __rmul__ as well as __mul__ on Proxy objects.
test/genini.py:
Default value for -EFOO should be True not 1 (since 1 is no longer
convertable to Bool).
--HG--
extra : convert_revision : f8a221fcd9e095fdd7b7db4be0ed0cdcd20074be
sim/serialize.hh:
Add variables to keep track of the number of checkpoints
dropped and maximum allowed.
--HG--
extra : convert_revision : 32241b90c58def6958ec84c53cc2cca996007506
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
SConscript:
Add GHB prefetcher to build list
python/m5/objects/BaseCache.mpy:
Add parameters about when to remove prefetches and wether or not to use cpuid to differentiate access patterns
--HG--
extra : convert_revision : 1d3fef21910f2f34b8c28d01b5f6e86eef53357c
